Good day, hackers.
Architecture Reference Manual for ARMv8 B2.2.1 [1] states:
For explicit memory effects generated from an Exception level the
following rules apply:
- A read that is generated by a load instruction that loads a single
general-purpose register and is aligned to the size of the read in the
instruction is single-copy atomic.
- A write that is generated by a store instruction that stores a single
general-purpose register and is aligned to the size of the write in the
instruction is single-copy atomic.
So I believe it is safe to define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY
for aarch64
[1] https://documentation-service.arm.com/static/61fbe8f4fa8173727a1b734ehttps://developer.arm.com/documentation/ddi0487/latest
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regards
Yura Sokolov
Postgres Professional
[email protected][email protected]
