Changeset 206539 in webkit for trunk/Source/JavaScriptCore/disassembler

Timestamp:

Sep 28, 2016, 1:30:44 PM (9 years ago)

Author:

[email protected]

Message:

Optimize B3->Air lowering of Fence on ARM
​https://bugs.webkit.org/show_bug.cgi?id=162342

Reviewed by Geoffrey Garen.

This gives us comprehensive support for standalone fences on x86 and ARM. The changes are as
follows:

• Sets in stone the rule that the heaps of a B3::Fence tell you what the fence protects. If the fence reads, it protects motion of stores. If the fence writes, it protects motion of loads. This allows us to express for example load-load fences in a portable way: on x86 they will just block B3 optimizations and emit no code, while on ARM you will get some fence.

• Adds comprehensive support for WTF-style fences in the ARM assembler. I simplified it just a bit to match what B3, the main client, knows. There are three fences: MemoryFence, StoreFence, and LoadFence. On x86, MemoryFence is ortop while StoreFence and LoadFence emit no code. On ARM64, MemoryFence and LoadFence are dmb ish while StoreFence is dmb ishst.

• Tests! To test this, I needed to teach the disassembler how to disassemble dmb ish and dmb ishst. I think that the canonical way to do it would be to create a group for dmb and then teach that group how to decode the operands. But I don't actually know what are all of the ways of encoding dmb, so I'd rather that unrecognized encodings fall through to the ".long blah" bailout. So, this creates explicit matching rules for "dmb ish" and "dmb ishst", which is the most conservative thing we can do.

• assembler/ARM64Assembler.h:

(JSC::ARM64Assembler::dmbISH):
(JSC::ARM64Assembler::dmbISHST):
(JSC::ARM64Assembler::dmbSY): Deleted.

• assembler/MacroAssemblerARM64.h:

(JSC::MacroAssemblerARM64::memoryFence):
(JSC::MacroAssemblerARM64::storeFence):
(JSC::MacroAssemblerARM64::loadFence):

• assembler/MacroAssemblerX86Common.h:

(JSC::MacroAssemblerX86Common::storeFence):
(JSC::MacroAssemblerX86Common::loadFence):

• b3/B3FenceValue.h:
• b3/B3LowerToAir.cpp:

(JSC::B3::Air::LowerToAir::lower):

• b3/air/AirOpcode.opcodes:
• b3/testb3.cpp:

(JSC::B3::testMemoryFence):
(JSC::B3::testStoreFence):
(JSC::B3::testLoadFence):
(JSC::B3::run):
(JSC::B3::testX86MFence): Deleted.
(JSC::B3::testX86CompilerFence): Deleted.

• disassembler/ARM64/A64DOpcode.cpp:

(JSC::ARM64Disassembler::A64DOpcodeDmbIsh::format):
(JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::format):

• disassembler/ARM64/A64DOpcode.h:

(JSC::ARM64Disassembler::A64DOpcodeDmbIsh::opName):
(JSC::ARM64Disassembler::A64DOpcodeDmbIshSt::opName):

Location:

trunk/Source/JavaScriptCore/disassembler/ARM64

Files:

• A64DOpcode.cpp (modified) (3 diffs)
• A64DOpcode.h (modified) (2 diffs)

trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp

@@ -1 +1 @@
 /*
- * Copyright (C) 2012 Apple Inc. All rights reserved.
+ * Copyright (C) 2012, 2016 Apple Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -85 +85 @@
     OPCODE_GROUP_ENTRY(0x15, A64DOpcodeCompareAndBranchImmediate),
     OPCODE_GROUP_ENTRY(0x15, A64DOpcodeHint),
+    OPCODE_GROUP_ENTRY(0x15, A64DOpcodeDmbIsh),
+    OPCODE_GROUP_ENTRY(0x15, A64DOpcodeDmbIshSt),
     OPCODE_GROUP_ENTRY(0x16, A64DOpcodeUnconditionalBranchImmediate),
     OPCODE_GROUP_ENTRY(0x16, A64DOpcodeUnconditionalBranchRegister),
@@ -824 +826 @@
 }
 
+const char* A64DOpcodeDmbIsh::format()
+{
+    appendInstructionName("dmb");
+    appendString("ish");
+    return m_formatBuffer;
+}
+
+const char* A64DOpcodeDmbIshSt::format()
+{
+    appendInstructionName("dmb");
+    appendString("ishst");
+    return m_formatBuffer;
+}
+
 // A zero in an entry of the table means the instruction is Unallocated
 const char* const A64DOpcodeLoadStore::s_opNames[32] = {

trunk/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h

@@ -1 +1 @@
 /*
- * Copyright (C) 2012 Apple Inc. All rights reserved.
+ * Copyright (C) 2012, 2016 Apple Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -510 +510 @@
 };
 
+class A64DOpcodeDmbIsh : public A64DOpcode {
+public:
+    static const uint32_t mask = 0xffffffff;
+    static const uint32_t pattern = 0xd5033bbf;
+
+    DEFINE_STATIC_FORMAT(A64DOpcodeDmbIsh, thisObj);
+
+    const char* format();
+
+    const char* opName() { return "dmb"; }
+};
+
+class A64DOpcodeDmbIshSt : public A64DOpcode {
+public:
+    static const uint32_t mask = 0xffffffff;
+    static const uint32_t pattern = 0xd5033abf;
+
+    DEFINE_STATIC_FORMAT(A64DOpcodeDmbIshSt, thisObj);
+
+    const char* format();
+
+    const char* opName() { return "dmb"; }
+};
+
 class A64DOpcodeLoadStore : public A64DOpcode {
 private: