Changeset 290907 in webkit for trunk/Source/JavaScriptCore/assembler

Timestamp:

Mar 7, 2022, 1:55:08 PM (3 years ago)

Author:

Angelos Oikonomopoulos

Message:

AssemblyHelpersSpoolers: use load/store pair on ARMv7
​https://bugs.webkit.org/show_bug.cgi?id=235112

Reviewed by Žan Doberšek.

Save ~1% code size for baseline JIT on JS2 by emitting load/store pair
instructions on 32-bit ARM.

• assembler/ARMv7Assembler.h:

(JSC::ARMv6Assembler::vldmia):
(JSC::ARMv7Assembler::vstmia):

• assembler/CPU.h:

(JSC::isARM):

• assembler/MacroAssemblerARMv7.h:

(JSC::MacroAssemblerARMv7::loadPair64):
(JSC::MacroAssemblerARMv7::storePair64):

• jit/AssemblyHelpers.cpp:

(JSC::AssemblyHelpers::copyLLIntBaselineCalleeSavesFromFrameOrRegisterToEntryFrameCalleeSavesBuffer):

• jit/AssemblyHelpersSpoolers.h:

(JSC::AssemblyHelpers::LoadRegSpooler::executePair):
(JSC::AssemblyHelpers::StoreRegSpooler::executePair):
(JSC::AssemblyHelpers::CopySpooler::CopySpooler):
(JSC::AssemblyHelpers::CopySpooler::loadPair):
(JSC::AssemblyHelpers::CopySpooler::storePair):

Location:

trunk/Source/JavaScriptCore/assembler

Files:

• ARMv7Assembler.h (modified) (3 diffs)
• CPU.h (modified) (1 diff)
• MacroAssemblerARMv7.h (modified) (1 diff)

trunk/Source/JavaScriptCore/assembler/ARMv7Assembler.h

@@ -584 +584 @@
         OP_VMOV_CtoD    = 0xEC00,
         OP_VMOV_DtoC    = 0xEC10,
+        OP_VSTMIA       = 0xEC80,
+        OP_VLDMIA       = 0xEC90,
         OP_FSTS         = 0xED00,
         OP_VSTR         = 0xED00,
@@ -689 +691 @@
         OP_VCVTSD_T1b    = 0x0A40,
         OP_VCVTDS_T1b    = 0x0A40,
+        OP_VSTMIAb       = 0x0B00,
+        OP_VLDMIAb       = 0x0B00,
         OP_NOP_T2b       = 0x8000,
         OP_DMB_SY_T1b    = 0x8F5F,
@@ -1926 +1930 @@
     }
 #endif
+
+    void vldmia(RegisterID rn, FPDoubleRegisterID rs, uint32_t count)
+    {
+        ASSERT(count < 16);
+        m_formatter.vfpMemOp(OP_VLDMIA, OP_VLDMIAb, true, rn, rs, count << 3);
+    }
+
+    void vstmia(RegisterID rn, FPDoubleRegisterID rs, uint32_t count)
+    {
+        ASSERT(count < 16);
+        m_formatter.vfpMemOp(OP_VSTMIA, OP_VSTMIAb, true, rn, rs, count << 3);
+    }
 
     void vand(FPDoubleRegisterID rd, FPDoubleRegisterID rn, FPDoubleRegisterID rm)

trunk/Source/JavaScriptCore/assembler/CPU.h

@@ -37 +37 @@
 {
 #if HAVE(ARM_IDIV_INSTRUCTIONS)
+    return true;
+#else
+    return false;
+#endif
+}
+
+constexpr bool isARM()
+{
+#if CPU(ARM)
     return true;
 #else

trunk/Source/JavaScriptCore/assembler/MacroAssemblerARMv7.h

@@ -935 +935 @@
     }
 
+    void loadPair64(RegisterID src, TrustedImm32 offset, FPRegisterID dest1, FPRegisterID dest2)
+    {
+        ASSERT(dest1 != dest2);
+        if ((dest2 == (dest1 + 1)) && !offset.m_value) {
+            // Only emit a VLDMIA if the registers happen to be consecutive and
+            // in the proper order and the offset happens to be zero. Otherwise,
+            // the extra instructions to adjust things mean there are no space
+            // savings and the VLDM itself might be a performance loss.
+            m_assembler.vldmia(src, dest1, 2);
+        } else {
+            loadDouble(Address(src, offset.m_value), dest1);
+            loadDouble(Address(src, offset.m_value + 8), dest2);
+        }
+    }
+
+    void storePair64(FPRegisterID src1, FPRegisterID src2, RegisterID dest, TrustedImm32 offset)
+    {
+        if ((src2 == (src1 + 1)) && !offset.m_value) {
+            // Only emit a VSTMIA under a narrow set of conditions. See
+            // loadPair64 for the rationale.
+            m_assembler.vstmia(dest, src1, 2);
+        } else {
+            storeDouble(src1, Address(dest, offset.m_value));
+            storeDouble(src2, Address(dest, offset.m_value + 8));
+        }
+    }
+
     void store32(RegisterID src, Address address)
     {