Changeset 50981 in webkit for trunk/JavaScriptCore/assembler

Timestamp:

Nov 13, 2009, 4:44:42 PM (16 years ago)

Author:

[email protected]

Message:

​https://bugs.webkit.org/show_bug.cgi?id=31050

Patch by Zoltan Herczeg <​[email protected]> on 2009-11-14
Reviewed by Gavin Barraclough.

Adding JSVALUE32_64 support for ARM (but not turning it
on by default). All optimizations must be disabled, since
this patch is only the first of a series of patches.

During the work, a lot of x86 specific code revealed and
made platform independent.
See revisions: 50531 50541 50593 50594 50595

• assembler/ARMAssembler.h:

(JSC::ARMAssembler::):
(JSC::ARMAssembler::fdivd_r):

• assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::lshift32):
(JSC::MacroAssemblerARM::neg32):
(JSC::MacroAssemblerARM::rshift32):
(JSC::MacroAssemblerARM::branchOr32):
(JSC::MacroAssemblerARM::set8):
(JSC::MacroAssemblerARM::setTest8):
(JSC::MacroAssemblerARM::loadDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::zeroDouble):

• jit/JIT.cpp:
• jit/JIT.h:
• jit/JITOpcodes.cpp:

(JSC::JIT::privateCompileCTIMachineTrampolines):

• jit/JITStubs.cpp:
• wtf/StdLibExtras.h:

Location:

trunk/JavaScriptCore/assembler

Files:

• ARMAssembler.h (modified) (2 diffs)
• MacroAssemblerARM.h (modified) (10 diffs)

trunk/JavaScriptCore/assembler/ARMAssembler.h

@@ -122 +122 @@
             MULL = 0x00c00090,
             FADDD = 0x0e300b00,
+            FDIVD = 0x0e800b00,
             FSUBD = 0x0e300b40,
             FMULD = 0x0e200b00,
@@ -401 +402 @@
         }
 
+        void fdivd_r(int dd, int dn, int dm, Condition cc = AL)
+        {
+            emitInst(static_cast<ARMWord>(cc) | FDIVD, dd, dn, dm);
+        }
+
         void fsubd_r(int dd, int dn, int dm, Condition cc = AL)
         {

trunk/JavaScriptCore/assembler/MacroAssemblerARM.h

@@ -121 +121 @@
     void lshift32(RegisterID shift_amount, RegisterID dest)
     {
-        ARMWord w = m_assembler.getImm(0x1f, ARMRegisters::S0, true);
-        ASSERT(!(w & ARMAssembler::OP2_INV_IMM));
-        m_assembler.ands_r(ARMRegisters::S0, shift_amount, w);
+        ARMWord w = ARMAssembler::getOp2(0x1f);
+        ASSERT(w != ARMAssembler::INVALID_IMM);
+        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
 
         m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
@@ -148 +148 @@
     }
 
+    void neg32(RegisterID srcDest)
+    {
+        m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2(0));
+    }
+
     void not32(RegisterID dest)
     {
@@ -165 +170 @@
     void rshift32(RegisterID shift_amount, RegisterID dest)
     {
-        ARMWord w = m_assembler.getImm(0x1f, ARMRegisters::S0, true);
-        ASSERT(!(w & ARMAssembler::OP2_INV_IMM));
-        m_assembler.ands_r(ARMRegisters::S0, shift_amount, w);
+        ARMWord w = ARMAssembler::getOp2(0x1f);
+        ASSERT(w != ARMAssembler::INVALID_IMM);
+        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
 
         m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0));
@@ -526 +531 @@
     }
 
+    Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
+    {
+        ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
+        or32(src, dest);
+        return Jump(m_assembler.jmp(ARMCondition(cond)));
+    }
+
     void breakpoint()
     {
@@ -567 +579 @@
         m_assembler.mov_r(dest, ARMAssembler::getOp2(0));
         m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
+    }
+
+    void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+    {
+        // ARM doesn't have byte registers
+        set32(cond, left, right, dest);
+    }
+
+    void set8(Condition cond, Address left, RegisterID right, RegisterID dest)
+    {
+        // ARM doesn't have byte registers
+        load32(left, ARMRegisters::S1);
+        set32(cond, ARMRegisters::S1, right, dest);
+    }
+
+    void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+    {
+        // ARM doesn't have byte registers
+        set32(cond, left, right, dest);
     }
 
@@ -580 +611 @@
     }
 
+    void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest)
+    {
+        // ARM doesn't have byte registers
+        setTest32(cond, address, mask, dest);
+    }
+
     void add32(Imm32 imm, RegisterID src, RegisterID dest)
     {
@@ -687 +724 @@
     }
 
+    void loadDouble(void* address, FPRegisterID dest)
+    {
+        m_assembler.ldr_un_imm(ARMRegisters::S0, (ARMWord)address);
+        m_assembler.fdtr_u(true, dest, ARMRegisters::S0, 0);
+    }
+
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
@@ -703 +746 @@
     }
 
+    void divDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        m_assembler.fdivd_r(dest, dest, src);
+    }
+
+    void divDouble(Address src, FPRegisterID dest)
+    {
+        ASSERT_NOT_REACHED(); // Untested
+        loadDouble(src, ARMRegisters::SD0);
+        divDouble(ARMRegisters::SD0, dest);
+    }
+
     void subDouble(FPRegisterID src, FPRegisterID dest)
     {
@@ -729 +784 @@
         m_assembler.fmsr_r(dest, src);
         m_assembler.fsitod_r(dest, dest);
+    }
+
+    void convertInt32ToDouble(Address src, FPRegisterID dest)
+    {
+        ASSERT_NOT_REACHED(); // Untested
+        // flds does not worth the effort here
+        load32(src, ARMRegisters::S1);
+        convertInt32ToDouble(ARMRegisters::S1, dest);
+    }
+
+    void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
+    {
+        ASSERT_NOT_REACHED(); // Untested
+        // flds does not worth the effort here
+        m_assembler.ldr_un_imm(ARMRegisters::S1, (ARMWord)src.m_ptr);
+        m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+        convertInt32ToDouble(ARMRegisters::S1, dest);
     }
 
@@ -767 +839 @@
         // If the result is zero, it might have been -0.0, and 0.0 equals to -0.0
         failureCases.append(branchTest32(Zero, dest));
+    }
+
+    void zeroDouble(FPRegisterID srcDest)
+    {
+        m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2(0));
+        convertInt32ToDouble(ARMRegisters::S0, srcDest);
     }