Changeset 59527 in webkit for trunk/JavaScriptCore/assembler

Timestamp:

May 15, 2010, 1:58:57 AM (15 years ago)

Author:

[email protected]

Message:

2010-05-15 Chao-ying Fu <​[email protected]>

Reviewed by Oliver Hunt.

Update MIPS JIT for unsigned right shift, Math.sqrt, load16
​https://bugs.webkit.org/show_bug.cgi?id=38412

Fixed MIPS build failure.

• assembler/MIPSAssembler.h: (JSC::MIPSAssembler::srl): (JSC::MIPSAssembler::srlv): (JSC::MIPSAssembler::sqrtd):
• assembler/MacroAssemblerMIPS.h: (JSC::MacroAssemblerMIPS::urshift32): (JSC::MacroAssemblerMIPS::sqrtDouble): (JSC::MacroAssemblerMIPS::load16): (JSC::MacroAssemblerMIPS::supportsFloatingPointSqrt):
• jit/JSInterfaceJIT.h:

Location:

trunk/JavaScriptCore/assembler

Files:

• MIPSAssembler.h (modified) (2 diffs)
• MacroAssemblerMIPS.h (modified) (4 diffs)

trunk/JavaScriptCore/assembler/MIPSAssembler.h

@@ -393 +393 @@
     }
 
+    void srl(RegisterID rd, RegisterID rt, int shamt)
+    {
+        emitInst(0x00000002 | (rd << OP_SH_RD) | (rt << OP_SH_RT)
+                 | ((shamt & 0x1f) << OP_SH_SHAMT));
+    }
+
+    void srlv(RegisterID rd, RegisterID rt, RegisterID rs)
+    {
+        emitInst(0x00000006 | (rd << OP_SH_RD) | (rt << OP_SH_RT)
+                 | (rs << OP_SH_RS));
+    }
+
     void lbu(RegisterID rt, RegisterID rs, int offset)
     {
@@ -548 +560 @@
         emitInst(0x44000000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
         copDelayNop();
+    }
+
+    void sqrtd(FPRegisterID fd, FPRegisterID fs)
+    {
+        emitInst(0x46200004 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
     }
 

trunk/JavaScriptCore/assembler/MacroAssemblerMIPS.h

@@ -320 +320 @@
     }
 
+    void urshift32(RegisterID shiftAmount, RegisterID dest)
+    {
+        m_assembler.srlv(dest, dest, shiftAmount);
+    }
+
+    void urshift32(Imm32 imm, RegisterID dest)
+    {
+        m_assembler.srl(dest, dest, imm.m_value);
+    }
+
     void sub32(RegisterID src, RegisterID dest)
     {
@@ -436 +446 @@
     }
 
+    void sqrtDouble(FPRegisterID src, FPRegisterID dst)
+    {
+        m_assembler.sqrtd(dst, src);
+    }
+
     // Memory access operations:
     //
@@ -608 +623 @@
     {
         return loadPtrWithPatchToLEA(address, dest);
+    }
+
+    /* Need to use zero-extened load half-word for load16.  */
+    void load16(ImplicitAddress address, RegisterID dest)
+    {
+        if (address.offset >= -32768 && address.offset <= 32767
+            && !m_fixedWidth)
+            m_assembler.lhu(dest, address.base, address.offset);
+        else {
+            /*
+                lui     addrTemp, (offset + 0x8000) >> 16
+                addu    addrTemp, addrTemp, base
+                lhu     dest, (offset & 0xffff)(addrTemp)
+              */
+            m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16);
+            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
+            m_assembler.lhu(dest, addrTempRegister, address.offset);
+        }
     }
 
@@ -772 +805 @@
 
     bool supportsFloatingPointTruncate() const
+    {
+#if WTF_MIPS_DOUBLE_FLOAT && WTF_MIPS_ISA_AT_LEAST(2)
+        return true;
+#else
+        return false;
+#endif
+    }
+
+    bool supportsFloatingPointSqrt() const
     {
 #if WTF_MIPS_DOUBLE_FLOAT && WTF_MIPS_ISA_AT_LEAST(2)