Changeset 66846 in webkit for trunk/JavaScriptCore/assembler

Timestamp:

Sep 6, 2010, 1:29:01 PM (15 years ago)

Author:

[email protected]

Message:

2010-09-06 Chao-ying Fu <​[email protected]>

Reviewed by Oliver Hunt.

Support JSVALUE32_64 on MIPS
​https://bugs.webkit.org/show_bug.cgi?id=43999

Add missing functions to support JSVALUE32_64 on MIPS.
Remove JSVALUE32 as the default for MIPS.

• assembler/MIPSAssembler.h: (JSC::MIPSAssembler::divd): (JSC::MIPSAssembler::mthc1): (JSC::MIPSAssembler::cvtwd):
• assembler/MacroAssemblerMIPS.h: (JSC::MacroAssemblerMIPS::neg32): (JSC::MacroAssemblerMIPS::branchOr32): (JSC::MacroAssemblerMIPS::set8): (JSC::MacroAssemblerMIPS::loadDouble): (JSC::MacroAssemblerMIPS::divDouble): (JSC::MacroAssemblerMIPS::convertInt32ToDouble): (JSC::MacroAssemblerMIPS::branchDouble): (JSC::MacroAssemblerMIPS::branchConvertDoubleToInt32): (JSC::MacroAssemblerMIPS::zeroDouble):
• jit/JIT.h:
• jit/JITOpcodes32_64.cpp: (JSC::JIT::privateCompileCTINativeCall):
• jit/JITPropertyAccess32_64.cpp: (JSC::JIT::privateCompilePutByIdTransition):
• jit/JITStubs.cpp: (JSC::JITThunks::JITThunks):
• jit/JITStubs.h:
• wtf/Platform.h:

Location:

trunk/JavaScriptCore/assembler

Files:

• MIPSAssembler.h (modified) (3 diffs)
• MacroAssemblerMIPS.h (modified) (9 diffs)

trunk/JavaScriptCore/assembler/MIPSAssembler.h

@@ -530 +530 @@
     }
 
+    void divd(FPRegisterID fd, FPRegisterID fs, FPRegisterID ft)
+    {
+        emitInst(0x46200003 | (fd << OP_SH_FD) | (fs << OP_SH_FS)
+                 | (ft << OP_SH_FT));
+    }
+
     void lwc1(FPRegisterID ft, RegisterID rs, int offset)
     {
@@ -561 +567 @@
     }
 
+    void mthc1(RegisterID rt, FPRegisterID fs)
+    {
+        emitInst(0x44e00000 | (fs << OP_SH_FS) | (rt << OP_SH_RT));
+        copDelayNop();
+    }
+
     void mfc1(RegisterID rt, FPRegisterID fs)
     {
@@ -580 +592 @@
     {
         emitInst(0x46800021 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
+    }
+
+    void cvtwd(FPRegisterID fd, FPRegisterID fs)
+    {
+        emitInst(0x46200024 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
     }
 

trunk/JavaScriptCore/assembler/MacroAssemblerMIPS.h

@@ -282 +282 @@
     }
 
+    void neg32(RegisterID srcDest)
+    {
+        m_assembler.subu(srcDest, MIPSRegisters::zero, srcDest);
+    }
+
     void not32(RegisterID srcDest)
     {
@@ -619 +624 @@
         m_fixedWidth = false;
         return label;
-    }
-
-    Label loadPtrWithAddressOffsetPatch(Address address, RegisterID dest)
-    {
-        return loadPtrWithPatchToLEA(address, dest);
     }
 
@@ -1303 +1303 @@
     }
 
+    Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
+    {
+        ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
+        if (cond == Signed) {
+            or32(src, dest);
+            // Check if dest is negative.
+            m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
+            return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
+        }
+        if (cond == Zero) {
+            or32(src, dest);
+            return branchEqual(dest, MIPSRegisters::zero);
+        }
+        if (cond == NonZero) {
+            or32(src, dest);
+            return branchNotEqual(dest, MIPSRegisters::zero);
+        }
+        ASSERT(0);
+        return Jump();
+    }
+
     // Miscellaneous operations:
 
@@ -1350 +1371 @@
         m_assembler.jr(MIPSRegisters::ra);
         m_assembler.nop();
+    }
+
+    void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+    {
+        set32(cond, left, right, dest);
+    }
+
+    void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+    {
+        move(right, immTempRegister);
+        set32(cond, left, immTempRegister, dest);
     }
 
@@ -1547 +1579 @@
     }
 
+    void loadDouble(const void* address, FPRegisterID dest)
+    {
+#if WTF_MIPS_ISA(1)
+        /*
+            li          addrTemp, address
+            lwc1        dest, 0(addrTemp)
+            lwc1        dest+1, 4(addrTemp)
+         */
+        move(ImmPtr(address), addrTempRegister);
+        m_assembler.lwc1(dest, addrTempRegister, 0);
+        m_assembler.lwc1(FPRegisterID(dest + 1), addrTempRegister, 4);
+#else
+        /*
+            li          addrTemp, address
+            ldc1        dest, 0(addrTemp)
+        */
+        move(ImmPtr(address), addrTempRegister);
+        m_assembler.ldc1(dest, addrTempRegister, 0);
+#endif
+    }
+
+
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
@@ -1610 +1664 @@
     }
 
+    void divDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        m_assembler.divd(dest, dest, src);
+    }
+
     void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
     {
         m_assembler.mtc1(src, fpTempRegister);
+        m_assembler.cvtdw(dest, fpTempRegister);
+    }
+
+    void convertInt32ToDouble(Address src, FPRegisterID dest)
+    {
+        load32(src, dataTempRegister);
+        m_assembler.mtc1(dataTempRegister, fpTempRegister);
+        m_assembler.cvtdw(dest, fpTempRegister);
+    }
+
+    void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
+    {
+        load32(src.m_ptr, dataTempRegister);
+        m_assembler.mtc1(dataTempRegister, fpTempRegister);
         m_assembler.cvtdw(dest, fpTempRegister);
     }
@@ -1668 +1741 @@
         }
         if (cond == DoubleNotEqual) {
-            m_assembler.ceqd(left, right);
+            m_assembler.cueqd(left, right);
             return branchFalse(); // false
         }
@@ -1690 +1763 @@
             m_assembler.cueqd(left, right);
             return branchTrue();
+        }
+        if (cond == DoubleNotEqualOrUnordered) {
+            m_assembler.ceqd(left, right);
+            return branchFalse(); // false
         }
         if (cond == DoubleGreaterThanOrUnordered) {
@@ -1723 +1800 @@
     }
 
+    // Convert 'src' to an integer, and places the resulting 'dest'.
+    // If the result is not representable as a 32 bit value, branch.
+    // May also branch for some values that are representable in 32 bits
+    // (specifically, in this case, 0).
+    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
+    {
+        m_assembler.cvtwd(fpTempRegister, src);
+        m_assembler.mfc1(dest, fpTempRegister);
+
+        // If the result is zero, it might have been -0.0, and the double comparison won't catch this!
+        failureCases.append(branch32(Equal, dest, MIPSRegisters::zero));
+
+        // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
+        convertInt32ToDouble(dest, fpTemp);
+        failureCases.append(branchDouble(DoubleNotEqualOrUnordered, fpTemp, src));
+    }
+
+    void zeroDouble(FPRegisterID dest)
+    {
+#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
+        m_assembler.mtc1(MIPSRegisters::zero, dest);
+        m_assembler.mthc1(MIPSRegisters::zero, dest);
+#else
+        m_assembler.mtc1(MIPSRegisters::zero, dest);
+        m_assembler.mtc1(MIPSRegisters::zero, FPRegisterID(dest + 1));
+#endif
+    }
+
 private:
     // If m_fixedWidth is true, we will generate a fixed number of instructions.