Topics tagged arm

Topic	Replies	Views	Activity
[RFC] [Clang] [ARM32] Compiler Support for Skip Fault Mitigation IR & Optimizations rfc , arm , clang , llvm	1	129	August 13, 2025
Clang and FDPIC on ARM? Using Clang arm	5	94	July 4, 2025
Instrumenting code after register allocation for ARM backends Common CodeGen Infrastructure arm , llvm	0	44	April 18, 2025
Senior Developer for Compilers and Static Analysis @ Samsung Research Poland Job Postings x86 , arm , riscv , clang , llvm	0	181	February 12, 2025
Adding function calls in Machine IR after Register Allocation Code Generation arm	1	78	January 31, 2025
Clang-tidy tries to analyze an STM32 assembly file located in compile_commands.json clang-tidy arm , clang	5	126	August 29, 2024
Clang + lld apparently can't find cross compile libraries LLD x86 , arm , clang , libc	9	364	June 10, 2024
Custom libc++ for C++20 coroutines on bare metal embedded Arm Beginners arm , libcxx	2	208	June 10, 2024
Setting -mcpu=cortex-a9 -mfpu=neon for ARM target does not make clang pick memcpy optimized for the co-processor Beginners arm	9	275	June 6, 2024
Cross-compilation from x86_64 to armv7 using Clang Using Clang arm	1	184	April 8, 2024
Does clang support to generate GOT-based position indenpendent code with pic-register? Using Clang arm , clang	9	1837	March 24, 2024
[RFC]: Strengthen Relaxed Atomics Implementation behind `-mstrict-rlx-atomics` Flag Code Generation arm , arm64 , powerpc , riscv , llvm	28	1720	December 22, 2023
Stack space allocation problem under different optimization levels of ARM IR & Optimizations arm , llvm	0	129	December 14, 2023
Bring features of fromelf of ARM to llvm-objcopy Beginners arm , llvm	13	717	November 28, 2023
SME in MLIR status (20/10/2023) MLIR arm , arm64 , mlir	1	599	October 20, 2023
How to substitute `SP` register with `R7` in Cortex-M code generation? Code Generation arm	4	338	October 6, 2023
[RFC] Creating a ArmSME Dialect MLIR arm , arm64	80	3603	June 9, 2023
How can I use the GCC sysroot for ARM when using Clang? Using Clang arm	2	1054	April 5, 2023
Why passing a structure by value is compiled into passing by reference without byval attribute? IR & Optimizations arm , arm64 , llvm	2	1237	November 28, 2022
Cross compilation of libcxx for baremetal ARMv7m with hard floating point support Beginners arm	9	1955	November 9, 2022
Why does march=native not work on Apple M1? Using Clang arm	7	6002	September 27, 2022
RFC: Removal of armv2/2A/3/3M target options Clang Frontend arm	2	630	September 8, 2022
[AArch64] How to combine a sequence IR cross BasicBlock? Beginners core , arm	2	435	September 7, 2022
Adding debug info to a raw binary Beginners arm	1	494	July 11, 2022
Clang SME ACLE intrinsics Clang Frontend arm , clang	1	876	June 27, 2022
[AArch64] Is the cost of MSUB instruction is significantly higher than that of the MADD instruction? IR & Optimizations arm	5	356	June 11, 2022
Is it time to start upstreaming the CHERI support to LLVM? LLVM Project core , arm , riscv	7	1556	May 9, 2022
Does the update of sp redundant in spill/reload code? Beginners arm , riscv	2	273	May 4, 2022
[AArch64] Does we need support value bigger than 2 for alloc_align Beginners arm , clang	2	265	April 7, 2022
Switching to GCC C runtime linkage for the baremetal driver Using Clang arm	6	1520	March 30, 2022