Changing from DP0 to DP1

Robotics & Edge Computing Jetson & Embedded Systems Jetson Xavier NX
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1

Hi,

I am working on a Xavier NX module on a custom board and want to change the display from from dp0 to dp1.

The NX has the following ports:
DP_AUX_CH0_HPD → SOR0;
DP_AUX_CH1_HPD → SOR1;
DP_AUX_CH2_HPD → SOR2;
DP_AUX_CH3_HPD-> SOR3;

What do Head0, Head1, Head2, and Head3 represent?

I need to understand the association between
HEAD0 → sor? HEAD1 → sor? HEAD2 → sor? HEAD3–> sor to the above DP_AUX channel

What head and sor are used to configure dp1?

Thanks
Malcolm

3

When I change the head0 or head1 to point to sor2, sor3 I get the result as attached

sor2 enabled others not enabled.
sor2 enabled others not enabled.786×437 14.1 KB

number 10
number 10810×523 41.2 KB

Malcolm’\

5

head0,1,2 indicate the nvdsiplay@xxxx node in the device tree.

SOR0 is mapping to DP0
SOR1 is mapaing to DP1

6

Hi WayneWWW

Our current setup is we have an LCD on DP0. It is setup as below. We simply want to have that from DP0 to DP1. Should I be able to replace sor0 with sor1 as shown in the figure below:

image
image887×336 20.3 KB

Are Other steps required?

Thanks
Malcolm

7

You could try to read how the current setup does first and then modify by yourself…
This whole thing is open source and not difficult thing, so you could try first.

After you change the dc-connector, you may still need to check if sor1 really has the setting you need.

8

And some other notes.
Please share your full schematic of display, Jetpack version and please do not share log in screenshot way.

Attach full text and your full dts converted back from dtb.

10

Attached is the device tree

Malcolm
device_tree.dtsi.txt (453.1 KB)

11

Hi

  1. Please also provide us the dmesg along with this dts. You should always give out things like that. If you provide a new dts, then give out corresponding dmesg too.

  2. I notice your schematic seems to be a LCD but not a external monitor. However, actually Xavier and Orin both do not really support eDP. The driver path may use the external DP case in current setup.

12

Here is the dmesg
dmesg.txt (79.7 KB)

13

Hi,

The device tree looks correct and dmesg shows that there is no monitor connected.

Please confirm if you configure the HPD pin of DP1 to be SFIO instead of GPIO. GPIO is for HDMI to use.

14

Hi WayneWWW,

I will verify the HPD pin and get back to you.

Malcolm

15

Hi,

I reviewed the pin assignments and HPD appears to be set correctly.

We are using Jetpack 5.12 and I would like to check that the configuration is correct on the board. I have used /sys/kernel/debug/tegra_pinctrl_reg, but I don’t see it.

Can you suggest what other files or tools I can use to verify the configuration on the device matches my .cfg files etc.

Thanks
Malcolm

16

Hi,

I think you better clarifying what kind of review you are doing there because I am not talking about hardware but just pinmux configuration. It is software setting under Linux_for_Tegra/bootloader/t186ref and Linux_for_Tegra/bootloader/.

You could also attach the pinmux file which you believe you are using.

17

We are using Jetpack 5.12 and I would like to check that the configuration is correct on the board. I have used /sys/kernel/debug/tegra_pinctrl_reg, but I don’t see it.

Some correction for your comment.

  1. There is no “5.12”. Only “5.1.2”.

  2. Don’t see what thing there? If you are talking about pinctrl, then you could check /sys/kernel/debug/pinctrl

18

tegra19x-mb1-pinmux-p3668-a01.cfg.txt (24.9 KB)

19

Hi,

Please help dump below info with your monitor connected

  1. sudo busybox devmem 0x02440038 #for dp_aux_ch1_hpd_pm1
  2. sudo busybox devmem 0x02212620 #for GPIO_M_ENABLE_CONFIG_01_0
  3. cat /sys/kernel/debug/tegra_dp*/dpaux_regs
20

Here are the results. I do not see a degra_dp1.

test@localhost:~$ sudo busybox devmem 0x02440038
0x00000411
test@localhost:~$ sudo busybox devmem 0x02212620
0x00000000
test@localhost:~$ sudo cat /sys/kernel/debug/tegra_dp0/dpaux_regs
DPAUX_INTR_EN_AUX 001 00000007
DPAUX_INTR_AUX 005 00000000
DPAUX_DP_AUXADDR 029 00000000
DPAUX_DP_AUXCTL 02d 00000000
DPAUX_DP_AUXSTAT 031 00000000
DPAUX_HPD_CONFIG 03d 07d000fa
DPAUX_HPD_IRQ_CONFIG 041 000000fa
DPAUX_DP_AUX_CONFIG 045 00000190
DPAUX_HYBRID_PADCTL 049 000024b2
DPAUX_HYBRID_SPARE 04d 00000000

21

This result seems not correct as bit 1:0 should be 0.

image
image386×142 3.44 KB

22

Yes. I noticed that. What would cause this?

Thoughts:

  1. Is the cfg file not updated into the correct (or am I missing updating a) folder in the build environment?
  2. Is there any stage in the boot process that may prevent this bit from getting set?

Malcolm

23

Hi,

In your previous device tree that shared with us, actually your dp_aux_ch1_hpd_pm1 is still set to RSVD. So please make sure they are aligned with your cfg.

And you could check your flash log and make sure it really the cfg file you modified that got in use.
I won’t know if that file got flashed on your side. You have to read the flash log by yourself to confirm that.