We use Xavier NX module to our customer carrier board, and schematic connect DP port to DP output screen.
We install Jetpack 5.1.2 to our Xavier NX carrier board, and it could bootup and login by UART port, but it no DP output to the screen.
The Jetpack 5.1.2 default is HDMI output for Xavier NX module.
How to modify Jetpack 5.1.2 to DP output on our Xavier NX carrier board?
The device tree provides 2 examples. One for DP and another one for HDMI.
If you want the HDMI one to be DP,
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Refer to the DP part and convert the HDMI part to DP mode in device tree.
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Make the hotplug gpio pinmux from GPIO to SFIO by using the pinmux spreadsheet.
Our schematic of Xavier NX customer carrier board design :
Xavier NX module DP1 port → DP connector
I see the dmesg log after Jetpack 5.1.2 bootup, and xavier-nx use the tegra194-p3668-0001-p3509-0000.dts.
[ 0.007172] DTS File Name: ../arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t19x/jakku/kernel-dts/tegra194-p3668-0001-p3509-0000.dts
I check the tegra194-p3668-0001-p3509-0000.dts, and the dts include tegra194-p3509-disp.dtsi for display, and I see the sor0 is sor0_dp_display and sor1 is sor1_hdmi_display.
[ /hardware/nvidia/platform/t19x/jakku/kernel-dts/tegra194-p3668-0001-p3509-0000.dts ]
#include "common/tegra194-p3668-common.dtsi"
#include "common/tegra194-p3509-0000-a00.dtsi"
[ /hardware/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3509-0000-a00.dtsi ]
#include "tegra194-p3509-disp.dtsi"
[ /hardware/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3509-disp.dtsi ]
&sor0 {
status = "okay";
nvidia,active-panel = <&sor0_dp_display>;
nvidia,sor-hdcp-not-supported;
};
&sor0_dp_display {
status = "okay";
nvidia,is_ext_dp_panel = <1>;
};
&sor1 {
status = "okay";
nvidia,active-panel = <&sor1_hdmi_display>;
nvidia,sor-hdcp-not-supported;
};
&sor1_hdmi_display {
status = "okay";
disp-default-out {
nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_LOW>;
};
};
How to setup the sor1 to DP display?
May I confirm below sor1 and sor1_dp_display setting are correct for DP1 port output DP?
&sor1 {
status = "okay";
nvidia,active-panel = <&sor1_dp_display>;
nvidia,sor-hdcp-not-supported;
};
&sor1_dp_display {
status = "okay";
nvidia,is_ext_dp_panel = <1>;
};
I attachd the tegra194-p3509-disp.dtsi.
tegra194-p3509-disp.zip (1.2 KB)
Yes, sor1_dp_display and sor1 is for DP1 pin to enable DP function.
I had update sor1 and sor1_dp_display to tegra194-p3509-disp.dtsi, and rebuild dtb, and re-falash image to Xavier NX.
tegra194-p3509-disp.dtsi
&sor1 {
status = "okay";
nvidia,active-panel = <&sor1_dp_display>;
nvidia,sor-hdcp-not-supported;
};
&sor1_hdmi_display {
status = "disabled";
disp-default-out {
nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_LOW>;
};
};
&sor1_dp_display {
status = "okay";
nvidia,is_ext_dp_panel = <1>;
};
But the Xavier NX DP1 port still no output DP on our customer carrier board.
Which .dtsi I need to check the DP1_HPD(pin 96) pinmux setting for DP hotplug?
I can’t find the dp_aux_ch1_hpd_pm1 setting in any .dtsi.
I attached my kernel log(jetpack5.1.2_xavier_nx_dp1_no_dp_output_kernel_dmesg
jetpack5.1.2_xavier_nx_dp1_no_dp_output_kernel_dmesg_log.txt (58.6 KB)
_log.txt).
please refer to this for how to configure pinmux.
Q1.
I can get tegra19x-jetson_xavier_nx_module-pinmux.dtsi, tegra19x-jetson_xavier_nx_module-gpio-default.dtsi, tegra19x-jetson_xavier_nx_module-padvoltage-default.dtsi after generate from pinmux excel.
But pinmux-dts2cfg.py need to know which PINMUX_DTS, GPIO_DTS for Xavier NX:
python pinmux-dts2cfg.py [--pinmux] ADDRESS_FILE GPIO_ADDRESS_FILE POR_VAL_FILE MANDATORY_PINMUX_FILE PINMUX_DTS GPIO_DTS VERSION
python pinmux-dts2cfg.py \
--pinmux \
addr_info.txt gpio_addr_info.txt por_val.txt \
--mandatory_pinmux_file mandatory_pinmux.txt \
tegra19x-p2888_galen_devkit-pinmux.dtsi \
tegra19x-p2888_galen_devkit-gpio-default.dtsi \
1.0 \
> galen.cfg
How to map these pinmux excel .dtsi to PINMUX_DTS, GPIO_DTS by pimux-dts2cfg.py in /Linux_for_Tegra/bootloader/t186ref/BCT?
python pimux-dts2cfg.py tegra19x-jetson_xavier_nx_module-pinmux.dtsi to which PINMUX_DTS, GPIO_DTS?
python tegra19x-jetson_xavier_nx_module-gpio-default.dtsi to which PINMUX_DTS, GPIO_DTS?
python tegra19x-jetson_xavier_nx_module-padvoltage-default.dtsi to which PINMUX_DTS, GPIO_DTS?
Q2. Which pinmux .cfg need to update for Xavier NX in /Linux_for_Tegra/bootloader?
In tegra194-p3509-disp.dtsi, I see the nvidia,dc-connector = <&sor1> of head0 and nvidia,dc-connector = <&sor0> of head0
&head0 {
status = "okay";
nvidia,fb-bpp = <32>;
nvidia,fbmem-size = <265420800>; /* 8K (7680*4320) 32bpp double buffered */ nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
win-mask = <0x7>;
nvidia,fb-win = <0>;
nvidia,dc-connector = <&sor1>;
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
avdd_hdmi-supply = <&p3668_spmic_sd0>; /* 1v0 */
avdd_hdmi_pll-supply = <&p3668_spmic_sd1>; /* 1v8 */
vdd_hdmi_5v0-supply = <&p3509_vdd_hdmi_5v0>; /* 5v0 */
};
&head1 {
status = "okay";
nvidia,fb-bpp = <32>;
nvidia,fbmem-size = <265420800>; /* 8K (7680*4320) 32bpp double buffered */ nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
win-mask = <0x38>;
nvidia,fb-win = <3>;
nvidia,dc-connector = <&sor0>;
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
vdd-dp-pwr-supply = <&p3668_spmic_sd0>;
avdd-dp-pll-supply = <&p3668_spmic_sd1>;
vdd-edp-sec-mode-supply = <&battery_reg>;
vdd-dp-pad-supply = <&battery_reg>;
vdd_hdmi_5v0-supply = <&p3509_vdd_hdmi_5v0>;
};
Could I need change head1 to sor1 for DP1 output DP?
&head0 {
status = "okay";
nvidia,fb-bpp = <32>;
nvidia,fbmem-size = <265420800>; /* 8K (7680*4320) 32bpp double buffered */ nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
win-mask = <0x7>;
nvidia,fb-win = <0>;
nvidia,dc-connector = <&sor0>;
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
avdd_hdmi-supply = <&p3668_spmic_sd0>; /* 1v0 */
avdd_hdmi_pll-supply = <&p3668_spmic_sd1>; /* 1v8 */
vdd_hdmi_5v0-supply = <&p3509_vdd_hdmi_5v0>; /* 5v0 */
};
&head1 {
status = "okay";
nvidia,fb-bpp = <32>;
nvidia,fbmem-size = <265420800>; /* 8K (7680*4320) 32bpp double buffered */ nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
win-mask = <0x38>;
nvidia,fb-win = <3>;
nvidia,dc-connector = <&sor1>;
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
vdd-dp-pwr-supply = <&p3668_spmic_sd0>;
avdd-dp-pll-supply = <&p3668_spmic_sd1>;
vdd-edp-sec-mode-supply = <&battery_reg>;
vdd-dp-pad-supply = <&battery_reg>;
vdd_hdmi_5v0-supply = <&p3509_vdd_hdmi_5v0>;
};
What the python tool does is convert the dtsi files you generated from the spreadsheet to a cfg file. Thus the input file is the first two dtsi files (tegra19x-jetson_xavier_nx_module-pinmux.dtsi, tegra19x-jetson_xavier_nx_module-gpio-default.dtsi,)
Python tool做的事情就是把你從excel spreadsheet建出來的pinmux/gpio dtsi 轉成cfg檔. 所以你要把建出來的那兩個dtsi當作input給python tool.
Q2. Which pinmux .cfg need to update for Xavier NX in /Linux_for_Tegra/bootloader?
You could refer to the board config you are using to flash. It will tell which pinmux cfg file is in use. The board config is under Linux_for_Tegra on your host PC.
你可以參考燒錄的時候使用的board config. 裡面有定義燒錄這一份板子會用上哪一個pinmux cfg. Board config就位在你跑flash.sh的那個Linux_for_Tegra目錄下
Could I need change head1 to sor1 for DP1 output DP?
head and sor are independent to each other. So actually no need to care about whether head1 is mapping to sor1 or not.
head 跟 sor是獨立的. 所以不需要head1一定得mapping給sor1.
I generate three .dtsi by Jetson_Xavier_NX_Pinmux_Configuration_Template_v1.06.xlsm, and put it to /Linux_for_Tegra/kernel/pinmux/t19x.
I get some ERROR message after send pinmux-dts2cfg.py command:
$ python pinmux-dts2cfg.py --pinmux addr_info.txt gpio_addr_info.txt por_val.txt --mandatory_pinmux_file mandatory_pinmux.txt \
tegra19x-jetson_xavier_nx_module-pinmux.dtsi tegra19x-jetson_xavier_nx_module-gpio-default.dtsi 1.0 > tegra19x-mb1-pinmux-p3668-a01.cfg
ERROR: pin dap3_sclk_pt1(0x00000440) field nvidia,enable-input(0x00000040) is not matching, val = 0x01 expected = 0x00
ERROR: pin dap3_fs_pt4(0x00000440) field nvidia,enable-input(0x00000040) is not matching, val = 0x01 expected = 0x00
ERROR: pin eqos_rd3_pf1(0x00022470) field nvidia,lpbk(0x00000020) is not matching, val = 0x01 expected = 0x00
ERROR: pin eqos_sma_mdio_pf4(0x00022440) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin sdmmc4_cmd(0x00002440) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin soc_gpio10_pg6(0x00000410) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00
ERROR: pin gp_pwm2_px2(0x00000410) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00
ERROR: pin uart2_tx_px4(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart2_rx_px5(0x00000450) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin can0_dout_paa2(0x0000c400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin can0_din_paa3(0x0000c450) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart3_tx_pcc5(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart3_rx_pcc6(0x00000450) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin soc_gpio22_pq2(0x00000459) field nvidia,pull(0x0000000c) is not matching, val = 0x02 expected = 0x00
ERROR: pin uart1_tx_pr2(0x00000400) field nvidia,pull(0x0000000c) is not matching, val = 0x00 expected = 0x02
ERROR: pin uart1_rx_pr3(0x00000454) field nvidia,pull(0x0000000c) is not matching, val = 0x01 expected = 0x02
We review pinmux setting in .cfg after pinmux-dts2cfg.py.
Xavier NX DP1 could DP output on our customer carrier board now.
Thanks for your support.
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