Skip to content
This repository was archived by the owner on Jun 26, 2020. It is now read-only.

Implement extractlane instruction for x86 #855

Merged
merged 4 commits into from
Aug 20, 2019
Merged

Implement extractlane instruction for x86 #855

merged 4 commits into from
Aug 20, 2019

Conversation

abrown
Copy link
Member

@abrown abrown commented Jul 17, 2019

The primary commit for this is 9785535 but the following three are improvements from comments to #833 or suggested by the IDE (9a036ec).

@abrown
Copy link
Member Author

abrown commented Jul 24, 2019

@sunfishcode can you take a look at this?

@abrown abrown mentioned this pull request Jul 24, 2019
Merged
@abrown abrown force-pushed the add-extract-lane-x86-rebased branch from dfa1ec7 to e6c6b90 Compare July 25, 2019 00:16
abrown
abrown commented Jul 25, 2019
View reviewed changes
@abrown abrown force-pushed the add-extract-lane-x86-rebased branch 2 times, most recently from 1b00fa6 to 2ead474 Compare July 26, 2019 22:37
@abrown
Copy link
Member Author

abrown commented Jul 26, 2019

As I was playing with clif-util run from #872 I realized that the recipe for extractlane could not be re-used for x86_pushd--the output operand for extractlane must be a gpr and the order of the registers passed to modrm_rr must be flipped. I fixed the tests to catch this and rebased the fixes in.

@bjorn3 bjorn3 mentioned this pull request Jul 27, 2019
Open
@abrown
Copy link
Member Author

abrown commented Aug 5, 2019

@arunetm, here is an extractlane implementation for x86.

abrown added 4 commits August 19, 2019 15:36
@abrown
Add x86 implementation of extractlane instruction
49f6d66
@abrown
Avoid unnecessary lane calculations in codegen code
ac74c3a 
This refactor moves the calculation of the number of lanes to code closer to where the Instruction/BoundInstruction is bound.
@abrown
Fix static analysis warnings
5fd8c91
@abrown
Remove SSE2 setting for x86
8bd1ff4 
In talking to @sunfishcode, he preferred to avoid the confusion of more ISA predicates by eliminating SSE2. SSE2 was released with the Pentium 4 in 2000 so it is unlikely that current CPUs would have SIMD enabled and not have this feature. I tried to note the SSE2-specific instructions with comments in the code.
@abrown abrown force-pushed the add-extract-lane-x86-rebased branch from 2ead474 to 8bd1ff4 Compare August 19, 2019 22:45
@abrown
Copy link
Member Author

abrown commented Aug 19, 2019

@sunfishcode this one is also rebased and ready for review

@sunfishcode sunfishcode self-requested a review August 19, 2019 23:17
@abrown abrown mentioned this pull request Aug 19, 2019
Merged
sunfishcode
sunfishcode approved these changes Aug 19, 2019
View reviewed changes
Copy link
Member

@sunfishcode sunfishcode left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good to me!

@sunfishcode sunfishcode merged commit 8977442 into bytecodealliance:master Aug 20, 2019
@abrown abrown deleted the add-extract-lane-x86-rebased branch August 21, 2019 16:14
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Reviewers
1 more reviewer

@sunfishcode sunfishcode sunfishcode approved these changes

Reviewers whose approvals may not affect merge requirements
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@abrown @sunfishcode