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compiler: Update all targets to the new c_int_width type
1 parent b88c006 commit 87feee9

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7 files changed

+7
-7
lines changed

7 files changed

+7
-7
lines changed

compiler/rustc_target/src/spec/base/xtensa.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ pub(crate) fn opts() -> TargetOptions {
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TargetOptions {
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os: "none".into(),
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endian: Endian::Little,
9-
c_int_width: "32".into(),
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c_int_width: 32,
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linker_flavor: LinkerFlavor::Gnu(Cc::Yes, Lld::No),
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executables: true,
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panic_strategy: PanicStrategy::Abort,

compiler/rustc_target/src/spec/targets/armv7_sony_vita_newlibeabihf.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ pub(crate) fn target() -> Target {
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options: TargetOptions {
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os: "vita".into(),
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endian: Endian::Little,
34-
c_int_width: "32".into(),
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c_int_width: 32,
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env: "newlib".into(),
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vendor: "sony".into(),
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abi: "eabihf".into(),

compiler/rustc_target/src/spec/targets/avr_none.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ pub(crate) fn target() -> Target {
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llvm_target: "avr-unknown-unknown".into(),
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pointer_width: 16,
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options: TargetOptions {
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c_int_width: "16".into(),
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c_int_width: 16,
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exe_suffix: ".elf".into(),
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linker: Some("avr-gcc".into()),
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eh_frame_header: false,

compiler/rustc_target/src/spec/targets/msp430_none_elf.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
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arch: "msp430".into(),
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options: TargetOptions {
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c_int_width: "16".into(),
19+
c_int_width: 16,
2020

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// The LLVM backend currently can't generate object files. To
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// workaround this LLVM generates assembly files which then we feed

compiler/rustc_target/src/spec/targets/xtensa_esp32_espidf.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ pub(crate) fn target() -> Target {
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options: TargetOptions {
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endian: Endian::Little,
16-
c_int_width: "32".into(),
16+
c_int_width: 32,
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families: cvs!["unix"],
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os: "espidf".into(),
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env: "newlib".into(),

compiler/rustc_target/src/spec/targets/xtensa_esp32s2_espidf.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ pub(crate) fn target() -> Target {
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options: TargetOptions {
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endian: Endian::Little,
16-
c_int_width: "32".into(),
16+
c_int_width: 32,
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families: cvs!["unix"],
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os: "espidf".into(),
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env: "newlib".into(),

compiler/rustc_target/src/spec/targets/xtensa_esp32s3_espidf.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ pub(crate) fn target() -> Target {
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options: TargetOptions {
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endian: Endian::Little,
16-
c_int_width: "32".into(),
16+
c_int_width: 32,
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families: cvs!["unix"],
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os: "espidf".into(),
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env: "newlib".into(),

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