You're reading from LLVM Code Generation A deep dive into compiler backend development

Product type Paperback

Published in May 2025

Publisher Packt

ISBN-13 9781837637782

Length 620 pages

Edition 1st Edition

Languages

C++

Tools

LLVM

Concepts

Programming Language

Author (1):

Quentin Colombet

View More author details

Table of Contents (30) Chapters

Preface

1. Part 1: Getting Started with LLVM

2. Building LLVM and Understanding the Directory Structure FREE CHAPTER

3. Contributing to LLVM

4. Compiler Basics and How They Map to LLVM APIs

5. Writing Your First Optimization

6. Dealing with Pass Managers

7. TableGen – LLVM Swiss Army Knife for Modeling

8. Part 2: Middle-End: LLVM IR to LLVM IR

9. Understanding LLVM IR

10. Survey of the Existing Passes

11. Introducing Target-Specific Constructs

12. Hands-On Debugging LLVM IR Passes

13. Part 3: Introduction to the Backend

14. Getting Started with the Backend

15. Getting Started with the Machine Code Layer

16. The Machine Pass Pipeline

17. Part 4: LLVM IR to Machine IR

18. Getting Started with Instruction Selection

19. Instruction Selection: The IR Building Phase

20. Instruction Selection: The Legalization Phase

21. Instruction Selection: The Selection Phase and Beyond

22. Part 5: Final Lowering and Optimizations

23. Instruction Scheduling

24. Register Allocation

25. Lowering of the Stack Layout

26. Getting Started with the Assembler

27. Unlock Your Book’s Exclusive Benefits

28. Other Books You May Enjoy

29. Index

Understanding the generic Machine IR

GlobalISel works directly on the Machine IR that you learned about in Chapter 11, except that it has a slightly different flavor, called generic Machine IR. The goal of the whole GlobalISel pipeline is to remove this generic flavor from the Machine IR to reach plain Machine IR at the end of the InstructionSelect pass.

The generic Machine IR differs from the regular Machine IR in two aspects:

The virtual registers may not have a register class. Instead, they have a type and, optionally, a register bank. Virtual registers that do not have a register class are called generic virtual registers.
The opcode of MachineInstr instances can use generic Machine IR opcodes easily identifiable by their G_ prefix. For instance, a generic addition instruction uses the G_ADD opcode. These opcodes are defined in the llvm/include/llvm/Target/GenericOpcodes.td file.

Note

The only difference between a regular and a generic...