Describing registers
As explained in Chapter 6, everything related to modeling a target goes through a TableGen backend. Unsurprisingly, this means that describing the registers of a target goes through this path as well. You’ll want to leverage this infrastructure because it will create the skeleton of your backend’s MCRegisterInfo and TargetRegisterInfo classes, as well as the iterators and enumerators for manipulating your registers and register classes.
Writing the target description
The process of modeling registers is supported by two TableGen classes, both defined in the ${LLVM_SRC}/lvm/include/llvm/Target/Target.td file.
The first one, known as the TableGen Register class, describes a register. For low-level modeling, you’ll find things such as its assembly name (via the AsmName field) or its encoding (via the HwEncoding field). You’ll also find higher-level concepts, such as its sub-registers (via the SubRegs fields) and the related...
