You're reading from LLVM Code Generation A deep dive into compiler backend development

Product type Paperback

Published in May 2025

Publisher Packt

ISBN-13 9781837637782

Length 608 pages

Edition 1st Edition

Languages

C++

Tools

LLVM

Concepts

Programming Language

Author (1):

Quentin Colombet

Preface

1. Getting Started with LLVM

2. Building LLVM and Understanding the Directory Structure FREE CHAPTER

3. Contributing to LLVM

4. Compiler Basics and How They Map to LLVM APIs

5. Writing Your First Optimization

6. Dealing with Pass Managers

7. TableGen – LLVM Swiss Army Knife for Modeling

8. Middle-End: LLVM IR to LLVM IR

9. Understanding LLVM IR

10. Survey of the Existing Passes

11. Introducing Target-Specific Constructs

12. Hands-On Debugging LLVM IR Passes

13. Introduction to the Backend

14. Getting Started with the Backend

15. Getting Started with the Machine Code Layer

16. The Machine Pass Pipeline

17. LLVM IR to Machine IR

18. Getting Started with Instruction Selection

19. Instruction Selection: The IR Building Phase

20. Instruction Selection: The Legalization Phase

21. Instruction Selection: The Selection Phase and Beyond

22. Final Lowering and Optimizations

23. Instruction Scheduling

24. Register Allocation

25. Lowering of the Stack Layout

26. Getting Started with the Assembler

27. Other Books You May Enjoy

28. Index

Overview of the instruction scheduling framework

The instruction scheduling framework in LLVM is made up of three main pieces. Let’s go through them one by one:

The data structure that represents the dependencies of the instructions to be scheduled. In the literature, this is called the data dependency graph (DDG), and in LLVM, it is represented with the ScheduleDAG class and its subclasses. At the code generation (codegen) level, you start with the ScheduleDAGInstrs subclass. Similar to what we explained in Chapter 14 for the directed-acyclic graph (DAG) instruction selection framework (also known as SDISel), this graph represents the producer/consumer data dependencies as well as the ordering constraints of the memory dependencies. In other words, this graph gives a relative order of the instructions, and a schedule is valid if and only if all these constraints are fulfilled. For instance, if there is an edge from node A toward node B, then B must appear before...