Summary
In this chapter, you learned how to implement the necessary target hooks to teach the LLVM register allocation infrastructure how to spill your registers. This is the only mandatory change to use the register allocation infrastructure.
Additionally, you learned how the register allocation pipeline is structured in LLVM with its coalescer and allocator running at two different stages of the codegen pipeline. Note that this is a simplification of how the register allocation pipeline works because, depending on the optimization level set by the frontend, different allocators may be used. For instance, the coalescer is not run when the optimization level is set to 0.
Next, we introduced you to the helper classes that provide the backbone of the liveness information used in LLVM. You learned that the slot indexes are a convenient way to uniquely identify the program points and that they are used to express the live intervals in a compact and intuitive way. The one quirk...
