This document describes the design and implementation of a programmable cardiac pacemaker using VHDL. It discusses how the pacemaker is divided into three main sections: a controlling unit, sensing unit, and pulse generator. The controlling unit and pulse generator are the main focus. Different pacing modes are implemented, including VOO, VVI, AAI, and DDD. The refractory period and AV delay timing features are also discussed. Simulation results validating the implementation of modes AOO, VOO, and DOO are shown. The pacemaker is designed to be programmable for different patients and conditions.