An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm

IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 07, 2014 | ISSN (online): 2321-0613
All rights reserved by www.ijsrd.com 413
An Efficient FPGA Implementation of the Advanced Encryption
Standard Algorithm
G. Mohan1
K. Rambabu 2
1
M.Tech 2
Assistant Professor
2
Department of Electronics and Communication Engineering
1,2
Brilliant Institute of Engineering and technology
Abstract— A proposed FPGA-based implementation of the
Advanced Encryption Standard (AES) algorithm is
presented in this paper. This implementation is compared
with other works to show the efficiency. The design uses an
iterative looping approach with block and key size of 128
bits, lookup table implementation of S -box. This gives low
complexity architecture and easily achieves low latency as
well as high throughput. Simulation results, performance
results are presented and compared with previous reported
designs.
Key words: AES, FPGA, encryption, decryption, Rijndael,
block cipher
I. INTRODUCTION
For a long time, the Data Encryption Standard (DES) was
considered as a standard for the symmetric key encryption.
DES has a key length of 56 bits. However, this key length is
currently considered small and can easily be broken. For this
reason, the National Institute of Standards and Technology
(NIST) opened a formal call for algorithms in September
1997. A group of fifteen AES candidate algorithms were
announced in August 1998. Next, all algorithms were
subject to assessment process performed by various groups
of cryptographic researchers all over the world. In August
2000, NIST selected five algorithms: Mars, RC6, Rijndael,
Serpent and Twofish as the final competitors. These
algorithms were subject to further analysis prior to the
selection of the best algorithm for the AES. Finally, on
October 2, 2000, NIST announced that the Rijndael
algorithm was the winner. Rijndael can be specified with
key and block sizes in any multiple of 32 bits, with a
minimum of 128 bits and a maximum of 256 bits. Therefore,
the problem of breaking the key becomes more difficult [1].
In cryptography, the AES is also known as Rijndael [2].
AES has a fixed block size of 128 bits and a key size of 128,
192 or 256 bits.
The AES algorithm can be efficiently implemented
by hardware and software. Software implementations cost
the smallest resources, but they offer a limited physical
security and the slowest process. Besides, growing
requirements for high speed, high volume secure
communications combined with physical security, hardware
implementation of cryptography takes place.
An FPGA implementation is an intermediate
solution between general purpose processors (GPPs) and
application specific integrated circuits (ASICs). It has
advantages over both GPPs and ASICs. It provides a faster
hardware solution than a GPP. Also, it has a wider
applicability than ASICs since its configuring software
makes use of the broad range of functionality supported by
the reconfigurable device [3].
This paper deals with an FPGA implementation of
an AES encryptor/decryptor using an iterative looping
approach with block and key size of 128 bits. Besides, our
design uses the lookup- table implementation of S-box. This
method gives very low complexity architecture and is easily
operated to achieve low latency as well as high throughput.
Organization of the rest of this paper is as follows.
Section 2 provides a brief overview of AES algorithm.
Design of AES based on FPGA implementation is presented
in section 3. Section 4 gives simulation results followed by
the comparisons with other works in section 5. Finally,
section 6 gives the conclusion of this work.
II. DESCRIPTION OF AES ALGORITHM
The AES algorithm is a symmetric block cipher that can
encrypt and decrypt information. Encryption converts data
to an unintelligible form called cipher-text. Decryption of
the cipher-text converts the data back into its original form,
which is called plain-text.
A. AES encryption
The AES algorithm operates on a 128-bit block of data and
executed Nr - 1 loop times. A loop is called a round and the
number of iterations of a loop, Nr, can be 10, 12, or 14
depending on the key length. The key length is 128, 192 or
256 bits in length respectively. The first and last rounds
differ from other rounds in that there is an additional
AddRoundKey transformation at the beginning of the first
round and no MixCoulmns transformation is performed in
the last round. In this paper, we use the key length of 128
bits (AES-128) as a model for general explanation. An
outline of AES encryption is given in Fig. 1.
B. SubBytes Transformation
The SubBytes transformation is a non-linear byte substitution,
operating on each of the state bytes independently. The
SubBytes transformation is done using a once-pre-calculated
substitution table called S-box. That S-box table contains 256
numbers (from 0 to 255) and their corresponding resulting
values. More details of the method of calculating the S-box
table refers to [4]. In this design, we use a look-up table as
shown in Table I. This is a more efficient method than
directly implementing the multiplicative inverse operation
followed by affine transformation.
This approach avoids complexity of hardware
plementation and has the significant advantage of
performing the S-box computation in a single clock cycle,
thus reducing the latency.

An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm
(IJSRD/Vol. 2/Issue 07/2014/092)
Table 1 S-Box
Table
Y
0 1 2 3 4 5 6 7 8 9 a B c d e f
0 6
3
7
c
7
7
7
b
f
2
6
b
6
f
c
5
3
0
1 6
7
2
b
f
e
d
7
a
b
7
6
1 c
a
8
2
c
9
7
d
f
a
5
9
4
7
f
0
a
d
d
4
a
2
A
f
9
c
a
4
7
2
c
0
2 b
7
f
d
9
3
2
6
3
6
3
f
f
7
C
c
3
4
a
5
e
5
f
1
7
1
d
8
3
1
1
5
3 4 c
7
2
3
c
3
1
8
9
6
5 9
a
7 1
2
8
0
e
2
e
b
2
7
b
2
7
5
4 9 8
3
2
c
1
a
1
b
6
e
5
a
a
0
5
2
3
b
d
6
b
3
2
9
e
3
2
f
8
4
5 5
3
d
1
0 e
d
2
0
f
c
b
1
5
b
6
a
c
b
b
e
3
9
4
a
4
c
5
8
c
f
6 d
0
e
f
a
a
f
b
4
3
4
d
3
3
8
5
4
5
f
9
2 7
f
5
0
3
c
9
f
a
8
X 7 5
1
a
3
4
0
8
f
9
2
9
d
3
8
f
5
b
c
b
6
d
a
2
1
1
0
f
f
f
3
d
2
8 c
d
0
c
1
3
e
c
5
f
9
7
4
4
1
7
c
4
a
7
7
e
3
d
6
4
5
d
1
9
7
3
9 6
0
8
1
4
f
d
c
2
2
2
a
9
0
8
8
4
6
e
e
b
8
1
4
d
e
5
e
0
b
d
b
a e
0
3
2
3
a
0
a
4
9
6 2
4
5
c
c
2
d
3
a
c
6
2
9
1
9
5
e
4
7
9
b e
7
c
8
3
7
6
d
8
d
d
5
4
e
a
9
6
c
5
6
f
4
E
a
6
5
7
a
a
e
8
c b
a
7
8
2
5
2
e
1
c
a
6
b
4
c
6
e
8
d
d
7
4
1
f
4
b
b
d
8
b
8
a
d 7
0
3
e
b
5
6
6
4
8
3 f
6
0
e
6
1
3
5
5
7
b
9
8
6
c
1
1
d
9
e
e e
1
f
8
9
8
1
1
6
9
d
9
8
e
9
4
9
b
1
e
8
7
e
9
c
e
5
5
2
8
d
f
f 8
c
a
1
8
9
0
d
b
f
e
6
4
2
6
8
4
1
9
9
2
d
0
f
b
0
5
4
b
b
1
6
C. ShiftRows Transformation
In ShiftRows transformation, the rows of the state are
cyclically left shifted over different offsets. Row 0 is not
shifted; row 1 is shifted one byte to the left; row 2 is shifted
two bytes to the left and row 3 is shifted three bytes to the
left.
D. MixColumns Transformation
In MixColumns transformation, the columns of the state are
considered as polynomials over GF (2
8
) and multiplied by
modulo x
4
+ 1 with a fixed polynomial c(x), given by:
c(x)={03}x
3
+ {01}x
2
+ {01}x + {02}.
E. AddRoundKey Transformation
In the AddRoundKey transformation, a Round Key is added
to the State - resulted from the operation of the MixColumns
transformation - by a simple bitwise XOR operation.
The RoundKey of each round is derived from the main key
using the KeyExpansion algorithm [1]. The
encryption/decryption algorithm needs eleven 128-bit
RoundKey, which are denoted RoundKey[0]
RoundKey[10] (the first RoundKey [0] is the main key).
B. AES decryption
Decryption is a reverse of encryption which inverse round
transformations to computes out the original plaintext of an
encrypted cipher-text in reverse order. The round
transformation of decryption uses the functions
AddRoundKey, InvMixColumns, InvShiftRows, and
InvSubBytes successively.
F. AddRoundKey
AddRoundKey is its own inverse function because the XOR
function is its own inverse. The round keys have to be
selected in reverse order. The description of the other
transformations will be given as follows.
G. InvShiftRows Transformation
InvShiftRows exactly functions the same as ShiftRows, only
in the opposite direction. The first row is not shifted, while
the second, third and fourth rows are shifted right by one,
two and three bytes respectively.
H. InvSubBytes transformation
The InvSubBytes transformation is done using a once-pre-
calculated substitution table called InvS-box. That InvS-box
table contains 256 numbers (from 0 to 255) and their
corresponding values. InvS-box is presented in Table II.
Table 1 Invs-Box
Table
Y
0 1 2 3 4 5 6 7 8 9 a b c d e f
0 5
2
9 6
a
d
5
3
0
3
6
a
5
3
8
b
f
4
0
a
3
9
e
8
1
f
3
d
7
f
b
1 7 e 3 8 9 2 f 8 3 8 4 4 c d e c

c 3 9 2 b f f 7 4 e 3 4 4 e 9 b
2 5
4
7
b
9
4
3
2
a
6
c
2
2
3
3
d
e
e
4
c
9
5
0
b
4
2
f
a
c
3
4
e
3 8 2
e
a
1
6
6
2
8
d
9
2
4
b
2
7
6
5
b
a
2
4
9
6
d
8
b
d
1
2
5
4 7
2
f
8
f
6
6
4
8
6
6
8
9
8
1
6
d
4
a
4
5
c
c
c
5
d
6
5
b
6
9
2
5 6
c
7
0
4
8
5
0
f
d
e
d
b
9
d
a
5
e
1
5
4
6
5
7
a
7
8
d
9
d
8
4
6 9
0
d
8
a
b
0 8
c
b
c
d
3
0
a
f
7
e
4
5
8
5 b
8
b
3
4
5
6
X 7 d
0
2
c
1
e
8
f
c
a
3
f
0
f
2 c
1
a
f
b
d
3 1 1
3
8
a
6
b
8 3
a
9
1
1
1
4
1
4
f
6
7
d
c
e
a
9
7
f
2
c
f
c
e
f
0
b
4
e
6
7
3
9 9
6
a
c
7
4
2
2
e
7
a
d
3
5
8
5
e
2
f
9
3
7
e
8
1
c
7
5
d
f
6
e
a 4
7
f
1
1
a
7
1
1
d
2
9
c
5
8
9
6
f
b
7
6
2
0
e
a
a
1
8
b
e
1
a
b f
c
5
6
3
e
4
b
c
6
d
2
7
9
2
0
9
a
d
b
c
0
f
e
7
8
c
d
5
a
f
4
c 1
f
d
d
a
8
3
3
8
8
7 c
7
3
1
b
1
1
2
1
0
5
9
2
7
8
0
e
c
5
f
d 6
0
5
1
7
f
a
9
1
9
b
5
4
a
0
d
2
d
e
5
7
a
9
f
9
3
c
9
9
c
e
f
e a
0
e
0
3
b
4
d
a
e
2
a
f
5
b
0
c
8
e
b
b
b
3
c
8
3
5
3
9
9
6
1
f 1
7
2
b
4 7
e
b
a
7
7
d
6
2
6
e
1
6
9
1
4
6
3
5
5
2
1
0
c
7
d
I. InvMixColumns Transformation
In the InvMixColumns transformation, the polynomials of
degree less than 4 over GF(2
8
), which coefficients are the
elements in the columns of the state, are multiplied modulo
(x
4
+ 1) by a fixed polynomial d(x) = {0B}x
3
+ {0D}x
2
+
{09}x + {0E}, where {0B}, {0D}; {09}, {0E} denote
hexadecimal values.
In the next section, a description of the proposed
design based on FPGA implementation of AES
encryption/decryption function is detailed.
III. FPGA IMPLEMENTATION OF AES ALGORITHM
Fig.2 shows the detailed design of AES core based on FPGA
implementation, where the control signals are described in
Table III.
The total design has 390 pins. It requires the
text_in, text_out and key which have a 128 bits length. And
the control signals using to control the proper operations of
the core are clk, reset_n, write, direction, done and enable
pins
The Key block loads keys and combines with Key
Round block to perform Key Expansion transformation, and
generates proper Roundkeys under the control signals from
the Controller block. Controller block takes write signal,
direction signal, and enable signal from outside and
generates all the control signals for the whole system.
TABL
E III.
CONTROL SIGNALS OF AES CORE
I/O Pin
Pin
name
numbe
r
Pin description
port
(bit)
clk I 1 Chip clock
reset_n I 1 Clear all signal
and data
write I 1 1: Write key and
text_in
directio
n
I 1 1: Encryption
0: Decryption
enable I 1 1: Enable AES core
0: Disable AES core
key I 128 Key data
text_in I 128 Plaintext/Ciphertext
data
done O 1 1:Encryption/Decryptio
n is
completed
text_out O 128 Ciphertext/ Plaintext
data
The plain text (text _in) and key is loaded only
when the write signal makes a low-high-low transition
(basically a pulse). The process is going to complete when
the done signal is pulsed after some clock cycles from the
write signal goes low. The “done” signal actives only in one
clock cycle.
Each round key as well as round is completed in
one clock cycle. However, the round key is finished before
the round is calculated by one clock cycle. Hence,
combining with one clock cycle for registering the input, a
total clock cycle need for processing 128-bit data is 13

clocks in encryption mode. In decryption, eleven round keys
must be completed before the first round is calculated.
Because the last round key is used in the first round process,
it takes 25 clock cycles to complete.
With using the above iterative looping approach, a
minimal number of clock cycles required performing
encryption/decryption for each data block of 128-bit
IV. SIMULATION RESULTS
The design has been coded by Verilog HDL. All the results
are synthesized and simulated basing on the Quatus 9.0, the
Model Sim – Altera 6.4a and EP20K400CB652C7 device
The results of simulating the encryption/decryption
algorithm from the ModelSim simulator are shown in Fig.3
and Fig 4.
Fig. 3: Timing simulation of AES encryption algorithm
Fig. 4: Timing simulation of AES decryption algorithm
They are showing a low latency. Hence, the
practical results are in accordance to theoretical predictions
and satisfy the encryption and decryption methodology. To
test the system, a test bench is used. The test bench applies
encryption/decryption input pulse to trigger the system. The
output result of the encryption was found accurately after 13
clock cycles from the starting of encryption process. So the
latency of encryption is only 13 clock cycles. Similarly, the
latency of decryption is 25 clock cycles.
V. COMPARISONS
In this section, the results obtained by our design, and
comparison between our results and other equivalent
implementations is given and discussed.
Our design for AES 128-bit encryption/decryption
algorithm was synthesized, implemented by Altera tools. Table
IV summarizes the hardware resources required by main
building blocks and gives detailed comparisons with the other
designs [5], [6]. Considering the comparison in table IV, our
design is found to be more efficient in terms of latency,
throughput and area. Therefore it allows us to process data in
communication applications requiring a high security
communication with low latency, high throughput and small
area. Besides, the design is compared with another
implementation using Xilinx chip [6] which uses the similar
architecture with our design, but it requires a higher latency.
Because Altera and Xilinx have the different chip
architectures,comparison between us and [6] cannot be done
in the other criteria of memory, throughput and area.
Table Iv.
Comparison In Fpga Implementations Of The
Aes
ALGORITHM
Designs Our design [5] [5] [6]
FPGA
Vendor
Altera Altera Altera Xilinx
APEX20K
APEX20K APEX20K
FPGA
Chip
C
(Mixed XCV600
C (Mixed
Version)
Version)
Memory
Encryption 40960 16384 16384 -
Decryption 42368 16384 16384 -
Latency Encryption 13 50 50 51
(Clock cycles) Decryption 25 50 50 51
Throughput Encryption 1188 240 187 -
(Mbps) Decryption 442 184 128 -
Area Encryption 895 2231 1998 -
(LCs) Decryption 1098 2548 1999 -
The design is tested with the sample vectors
provided by FIPS 197 [2]. The algorithm achieves a low
latency and the throughput reaches the value of
1054Mbit/sec for encryption and 615 Mbit/sec for
decryption.
VI. CONCLUSIONS
The Advanced Encryption Standard algorithm is a
symmetric block cipher that can process data blocks of 128
bits through the use of cipher keys with lengths of 128, 192,
and 256 bits. An efficient FPGA implementation of 128 bit
block and 128 bit key AES algorithm has been presented in
this paper. The design is implemented on Altera using
APEX20KC FPGA which is based on high performance
architecture. The proposed design is implemented based on
the iterative approach for cryptographic algorithms. Our
architecture is found to be better in terms of latency,
throughput as well as area. The design is tested with the
sample vectors provided by FIPS 197 [2]. The algorithm
achieves a low latency and the throughput reaches the value
of 1054Mbit/sec for encryption and 615 Mbit/sec for
decryption.

REFERENCE
[1] Daemen J., and Rijmen V, "The Design of Rijndael:
AES-the Advanced Encryption Standard", Springer-
Verlag, 2002
[2] FIPS 197, “Advanced Encryption Standard (AES)”,
November 26, 2001.
[3] Tessier, R., and Burleson, W., “Reconfigurable
computing for digital signal processing: a survey”,
J.VLSI Signal Process., 2001, 28, (1-2), pp.7-27.
[4] Ahmad, N.; Hasan, R.; Jubadi, W.M; “Design of
AES S-Box using combinational logic optimization”,
IEEE Symposium on Industrial Electronics &
Applications (ISIEA), pp. 696-699, 2010.
[5] Alex Panato, Marcelo Barcelos, Ricardo Reis, “An IP
of an Advanced Encryption Standard for Altera
Devices”, SBCCI 2002, pp. 197-202, Porto Alegre,
Brazil, 9 and 14 September 2002.
[6] Mr. Atul M. Borkar, Dr. R. V. Kshirsagar and Mrs.
M. V. Vyawahare, “FPGA Implementation of AES
Algorithm”, International Conference on Electronics
Computer Technology (ICECT), pp. 401-405, 2011
3rd
.

An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm

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An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm