Introduction to tms320c6745 dsp

Introduction and
Architecture of
TMS320C6745
M.K.Jeevarajan .M.E,(Ph.D)
https://www.pantechsolutions.net/products/dsp-dsc-
boards/tms320c6745-tyro

Technology beyond the Dreams™ Copyright © 2014 Pantech Prolabs India Pvt Ltd.
DAY 1
Two Day Workshop on TMS320C6745
DAY 1 - 27.04.2015
Session Time Class Topics Presenter
9.30-10.15 Inauguration
I 10.15- 11.15 Introduction to Texas DSP& Architecture M.K.Jeevarajan
11.15-11.30 Break
II
11.30-12.15 Introduction to CCS M.K.Jeevarajan
12.15-12.45 Creating and Debugging a Project In CCS, LED
Blinking, Switch Interface
M.K.Jeevarajan
01.00-02.00 Lunch Break
III 02.00-03.15 Waveform Generation M.K.Jeevarajan
03.15-03.30 Break
IV 03.30-04.15 UART Interface M.K.Jeevarajan
04.15 -04.30 Wrap-up - Q&A

DAY 2Two Day Workshop on TMS320C6745
DAY 2 - 28.04.2015
Session Time Class Topics Presenter
I 09.30- 10.45 Image processing using TMS320C6745 -PART 1
Median Filter
M.K.Jeevarajan
10.45-11.15 Break
II
11.15-12.00 Image processing using TMS320C6745 -PART 2
Discrete Wavelet Transform
M.K.Jeevarajan
12.00-12.45 Discrete Wavelet Transform
Linear Convolution, Circular Convolution
M.K.Jeevarajan
Paul Kannan
01.00-02.00 Lunch Break
III 02.00-03.15 FIR-Low pass and High Pass Filters Paul Kannan
03.15-03.30 Break
IV 03.30-04.30 Valedictory and Feedback

WHAT IS DSP ?
a bit loudAnalog Computer
Digital Computer
ADC
DSP
DAC OUTPUT
1010 1001

Digital Signal Processor is mathematics on chip.
 DSPs usually run applications with hard real-time constraints:
 DSPs usually process infinite continuous data streams.
Most of the DSP doses not have an Memory Management Unit
DSP processors are microprocessors designed for efficient
mathematical manipulation of digital signals.
Basic Features of
DSPs

• Microcontrollers are control oriented ,DSP are data path
oriented
• Use a GPP processor when the following are required:
– Large memory.
– Advanced operating systems.
• Use a DSP processor when the following are required:
– Precision
– Cost saving.
– Smaller size.
– Low power consumption.
– Processing of signals in real-time.
Why do we need DSP processors?

DSP Vs FPGA

Power Supply
CLKCLK
CLK
custom
IF-logic
SDRAM SDRAM
SRAM SRAMSRAM
Memory
Controller
UART
L
C
Display
Controller
Interrupt
Controller
Timer
Audio
Codec
CPU
(uP / DSP) Co-
Proc.
GP I/O
Address
Decode
Unit
Ethernet
MAC
Traditional embedded system
design using DSP

Next Step...Next Step...
FPGA
CLKCLK
CLK
custom
IF-logic
SDRAM SDRAM
SRAM SRAMSRAM
Memory
Controller
UART
Display
Controller
Timer
Power Supply
L
C
Audio
Codec
CPU
(uP / DSP) Co-
Proc.
GP I/O
Address
Decode
Unit
Ethernet
MAC
Interrupt
Controller

Power Supply
SDRAM SDRAMSRAM SRAMSRAM
L
C
Audio
Codec EPROM
Configurable system on Chip-
CSoC

 Higher Performance
Parallel algorithm implementation
 Customizable Design
Optimize for speed and cost
 System Integration
Less chips could mean less system cost
When to use DSP in FPGA

Comparison of DSP with Other
Processors and Controllers

Processor selection Criteria
 Development tools
 Performance
 Cost
 Operating systems
 Hardware tools
 Peripherals
 Power consumption
 Supplier reputation

What Problem Are We Trying
To Solve?
Digital sampling of
an analog signal:
A
t
Most DSP algorithms can be
expressed with MAC:
count
i = 1
Y = Σ coeffi * xi
for (i = 0; i < count; i++){
sum += c[i] * x[i]; }
DAC
x Y
ADC DSP

Typical DSP algorithms
• The Sum of Products (SOP) is the key element in most
DSP algorithms
• DSP’s are optimized to perform multiplication and addition
operations.
• Multiplication and addition are done in hardware and in one
cycle.
Convolution (mixing of signals)
Correlation (comparison of signals)
Transformation of signals (e.g. time to frequency domain)
 Filtering of signals

Algorithm Equation
Finite Impulse Response Filter
Infinite Impulse Response Filter
Convolution
Discrete Fourier Transform
Discrete Cosine Transform

Sum of Products – Flow Chart
No
Y
Requirements:
•Fast Multiply and
Accumulate(MAC)
•Pointer Update Mechanism
•Loop Counter
•Conditional Branch
x[0]
x[1]
x[i]
Acc
Yes
i≥0?
MPY
i=i-1
Add
Initial Conditions:
•*x points to x[0]
•*a points to a[0]
•Loop Counter = i-1

About Signal
• Bearers of information.
Examples :
speech, music, image, video, ECG, EEG, RADAR.., etc
• Function of independent variables such as time, space, position etc..,
One dimensional :
signal of time(ex: speech)
Two dimensional:
signal of space and position(ex: image)
Three dimensional
signal of space, position and time(ex:video)
Multi dimensional also

DSP is Everywhere
• Image processing
– Compression,segmentation,Video conferencing
• Medical
– Magnetic Resonance, Tomography, Electrocardiogram,
• Military
– Radar, Sonar, Space photographs, remote sensing,UAV
• Communication
– Modulation, coding, detection, equalization, echo cancellation,…
– Cell Phones, dial-up modem, DSL modem, Satellite Receiver,…
• Automotive
– ABS, GPS, Active Noise Cancellation, Cruise Control, Parking,…
• Mechanical
– Motor control, process control, oil and mineral prospecting,…

Sample Application-Music System

DSP Leading Manufacturers
1. Texas Instruments (TI)
2. Analog Devices (ADSP)
3. Motorola

Types of DSPs Processors
32-BIT FLOATING POINT (5% of market):
– TMS320C6000
– ANALOG DEVICES ADSP21xxx
16-BIT FIXED POINT (95% of market)
– TMS320C54XX,C2000
– ANALOG DEVICES ADSP21xx,Blackfin
Floating point DSP are meant for Precsion and accuracy

DSPs Evolution
• First generation (TI TMS32010)
• Second generation (Analog Dev. ADSP-2100, TI
TMS320C50)
• Third generation (TMS320C541)
• Fourth generation (TI TMS320C6201, TI
TMS320C6713, TI TMS320C6747)
23

First Generation (1982)
 In 1982 TI introduces its first
programmable DSP
 16-bit fixed-point
 Harvard architecture
 Accumulator
 Specialized instruction set
 Operating at 5 MIPS
 EXAMPLE : TMS320C10
25
5MIPS

Second Generation (1987)
• 24-bit data, instructions
• 1988 – First Floating Point DSP
(C3X)
• 3 memory spaces (X, Y, P)
• Modulo addressing
EXAMPLE : TI- TMS320C3x,
TMS320C50
26
20MIPS

Third Generation (1995)
• Enhanced conventional DSP architectures
• 3.0 or 3.3 volts
• More on-chip memory
• Application-specific function units in data path or as co-
processors
• More sophisticated debugging and application
development tools
EXAMPLE : TI TMS320C5416
27
160MIPS

Fourth Generation (1998)
• 32 – Bit floating point.
• Designed for REAL TIME PROCESSing easily.
• Operating Core Voltage : 1.8V
DSC (TMS320F2812) for Motor Control Applications
• VLIW-like architectures, achieve top performance via high
parallelism and increased clock speeds
• EXAMPLE : TI TMS320C6713,
28
600MIPS

2 or More Independent Processors in 1 Package
Symmetric Multiprocessing
 Number of Identical Processors
 Common Shared Memory
 One Operating System
Asymmetric Multiprocessing
 Different Processors, Instruction Sets
 Different Operating Systems
 Possibly Without Shared Memory
Multicore Processor

•Identical Cores
•Identical access to all System Resources
•Memory, Disk, UARTs, Communication Controllers
•Examples: Analog Devices Blackfin 561
SMP-BF561

Processors Need Not be Identical
Processor Specialization May Increase Performance.
T.I.’s OMAP•General Purpose Processor+Digital Signal Processor(“DSP”)
AMP-TI OMAP

Lowest Cost
Control Systems
• Storage
• Motor Control
Highest
Efficiency
Best MIPS per:
Watt / Dollar/ Size
• Wireless Clients
• Modems / Telephony
• VoIP
Highest
Performance
Multi Channel,
Multi Function
• Comm Infrastructure
• xDSL
• Imaging, Video
C6000
(C62x,C67x,C64x)
C3x C4x C8x
’C2000
(C20x,C24x,C28x)
C1x C2x
C5000
(C54x, C55x)
C5x
Different needs, ManyDifferent needs, Many
familiesfamilies
6

INSIDE A DSP ENGINE?

Architecture of the Digital Signal Processor

Features of c6745
• * Eight 32-Bit Instructions/Cycle
* 32/64-Bit Data Word
* 600-MHz Clock Rates
* 4.4-, 6.7-ns Instruction Cycle Time
* 1800 MIPS/1350 MFLOPS
* Rich Peripheral Set, Optimized for Audio
* Highly Optimized C/C++ Compiler
• Highest-Performance Floating-Point Digital
Signal Processor

TMS320C674x Architecture - Overview
Performance & Memory
Communications
• Up to 300MHz
• 256K L2 (up to 64K cache)
• 32K L1P & L1D Cache/SRAM
• 32-bit DDR2-266
• 16-bit EMIF (NAND Flash)
• 64-Channel EDMA 3.0
• 10/100 EMAC
• USB 1.1 & 2.0
• SATA
Power/Packaging
• 13x13mm nPBGA & 16x16mm
PBGA
• Pin-to-pin compatible w/OMAP
L138 (+ARM9), 361-pin pkg
• Dynamic voltage/freq scaling
• Total Power < 420mW
128K L3
16-bit EMIF
DDR2
mDDR
McASP
MMC/SD
EMAC
HPI
SATA
I2C, SPI,
SwitchedCentralResource(SCR)
256K
L2
EDMA3
C674x+ DSP Core
Floating-Pt CPU
32KB L1P Cache/SRAM
32KB L1D Cache/SRAM
4-32x
PLL
TMS320C674x
128
128
256
256
128
128
USB
Timers
LCD, PWM, eCAP
Fixed-Pt CPU
uPP

QFP
SOLDERING
IRON
SOLDERING
STATION
OVEN
Selection of DSP Packages
DIP SOIC
BGA
PLCC

C6745 Boot Modes - Overview
BOOT Modes
• NAND
• NOR
• HPI
• I2C
• SPI
• UART
ROM Code
0x11700000
0
1
2
3
BOOT[x]
On RESET:
• BOOT[x] pins are sampled
• Corresponding boot routine
is executed
Boot Loader (ARM or DSP):
• Runs out of L2 ROM
• Copies FLASH → RAM
• Execution begins at specified
“entry point” (reset vector)

Clock Cycle
What is a clock cycle?
C6000C6000
CLKIN
CLKOUT2 (½, ¼, or 1/6 CLKOUT1)
CLKOUT1 (C6000 clock cycle)
PLL
When we talk about
cycles ...
The time between successive instructions
CLKIN (MHz) PLL Rate CPU Clock Frequency CPU Clock Cycle
Time
MIPs (max)
60 x12 720 MHz 1.39 ns 5760
30 x10 300 MHz 3.33 ns 2400
50 x4 200 MHz 5 ns 1600
25 x4 100 MHz 10 ns 800

DSP
EDMA/USB/McASP/UART
/SPI/MMC/SD
EMIFA
I2C/GPIO
EMIFB
EMAC
OBSERVATION
CLOCK SOURCE
24 1
24+1
1+1
24 600
133
133
300

The C6000 Block Diagram

The C6000 DSP CPU Core
• The heart of the C6000 is the Central Processing
Unit (CPU).
• This is where the computations are carried out.

The C67x Data Paths
• The C67x CPU is
divided into two parallel
parts, Data path A and
Data path B.
• It is stereo.
• With this architecture, it
is possible to process
both left and right
channels of an audio
signal at the same time.

The Units
• Within the CPU are four units per data path:
– the L. Unit. Used for logical operations .
– the M. Unit. Used for carrying out multiplications.
– the S. Unit. Used for carrying out shifts.
– the D. Unit. Used to move data.
• At any time, it is possible to carry out an
operation in each of the L. M. S. and D. units.
• This means the processor can do up to 8 things
at once!

Functional Units and Operations
Performed

Register Files
• The C67x contains two sets of
16 ,32-bit registers.
• Operations within the C6000 are carried out
in two groups of 16 registers called
A0 to A15 and B0 to B15.
• All computations are done directly using these
registers.

C6000 Interfaces

The DSP interfaces are on the left in the
block diagram.

External Memory Interface (EMIF)
• The C6000 contains a limited amount of memory (RAM) on chip.
• The External Memory Interface (EMIF) allows access to external
memory (RAM).
• EMIFA is used to interface with SDRAM and Other Memories
• EMIFB is used to interface only with SDRAM
External RAM EMIF CPU
EMIF

EMIFA

EMIFB

Direct Memory Access (DMA)
• Direct Memory Access (DMA) provides an
efficient way to transfer data without using the
CPU.
• It is very useful for transferring large blocks of
data, for example video and audio.

Data Transfer without DMA
• Without Direct Memory Access (DMA), any data
transfer has to be handled by the CPU.

Data Transfer with DMA
• With DMA, data values are transferred directly to
memory.
• This enables the CPU to allocates its resources
for other tasks.

The McBSP
• The multi-channel
buffered serial peripheral
interfaces (McBSP) are
simple serial interfaces.
• They can be used as a
simple interface, in
particular to audio
ADCs/DACs.

The Timers
• The C6000 contains two
32-bit timer/counters
which can:
– transfer data at regular
intervals.
– generate physical outputs
(TOUT pin) to start
processes e.g. a robot.
– measure the timing of
external events via a
physical input (TINP pin).

How does an interrupt work?
• An everyday example of an interrupt is the
telephone.
• Imagine you are working at your desk.
– the phone rings
– you choose to answer the phone
– you then continue with your work.
• Short telephone conversation – slight delay to work.
• Long telephone conversation – can miss deadline!

Interrupts
• The C6000 CPU has a
range of interrupts.
• With interrupts you can
automatically send /
receive data, while
carrying out another
task.

Interrupt Priorities
• In the real world, there will be several interrupts
– telephone, fax, e-mail, pager, visitors.
• However, you can only do one thing at a time.
• Interrupts must therefore have a priority level:
– important tasks – high priority e.g. customer calls.
– less important tasks – low priority e.g. junk e-mails.

CPU Interrupt Priority
• Reset has highest
priority. It is equivalent to
“Ctl-Alt-Del” on a PC.
• NMI (non-maskable
interrupt) is next. You
might use this for an
emergency shutdown.

Instruction Set Features
* Single- and Double-Precision Instructions
* Byte-Addressable (8-, 16-, 32-Bit Data)
* 8-Bit Overflow Protection
* Saturation; Bit-Field Extract, Set, Clear; Bit-
Counting; Normalization

C67x Instruction Set

Summary
• What is DSP
• Basic features of DSP
• Need for DSP Processor,Diff between DSP,GPP,uController
• When to use DSP in FPGA
• Comparison
• Sum of Products
• Generation of DSP
• Multi core processors
• TI Variations-c2000,c5000,c6000
• Inside a DSP
• Diff between Von neumann,Harvard and Super Harvard
• TMS320C6746 Architecture
• Selection of DSP Packages

• Boot Modes
• Clock
• Configuring PLL
• Block diagram
• CPU core
• Data Paths
• Registers
• Units
• EMIF
• DMA
• Timers
• Interrupts
• Instruction set

?

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Introduction to tms320c6745 dsp

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