Design-for-Test (Testing of VLSI Design)
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This document provides an acknowledgement and thanks to various professors and scientists for their work that contributed to the content in this presentation on emerging technologies in testing. It then provides an overview of topics related to testing quality, economics of testing, testability, design-for-test, and different digital testing techniques including ad-hoc methods, structured methods like scan testing and built-in self-test (BIST).
![Scan Overheads
• IO pins: One pin necessary.
• Area overhead:
• Gate overhead = [4 nsff/(ng+10nff)] x 100%
where ng = comb. gates; nff = flip-flops
• More accurate estimate must consider
scan wiring and layout area.
• Performance overhead:
• Multiplexer delay added in combinational
path; approx. two gate-delays.
• Flip-flop output loading due to one
additional fanout; approx. 5 - 6%. 56
DrUshaMehta3December2019](https://image.slidesharecdn.com/20199testingandverificationofvlsidesigndft-191203043122/85/Design-for-Test-Testing-of-VLSI-Design-56-320.jpg)
Design-for-Test (Testing of VLSI Design)
- 2. Acknowledgement This presentation has been summarized from various books, papers, websites and presentations and so on …. all over the world. I couldn’t remember where these large pull of hints and work come from. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. I am thankful to them to make my teaching process more effective. 2 DrUshaMehta3December2019
- 4. Economics of Testing • Assumptions: • Sooner is better • Escapes are bad • Fewer tests means more escapes • Fixed budget so limited tests. • Efficiency: • Average tests per unit efforts • Effectiveness • Average Probability of detecting a bug per unit of effort • Higher Testability • More better tests, same cost • Lower Testability • Fewer / weaker tests, same cost 4 DrUshaMehta3December2019
- 5. Testability • We can easily test the circuit if we can easily control and observe the internal nodes. • Testability = Controllability + Observability • Controllability: The ability to apply inputs to circuit under test and place it in specified test • Obsevability: The ability to observe states and outputs 5 DrUshaMehta3December2019
- 6. Design-for-Test • Add controllability Observability to Circuit • Ease the test process • More support for test automation • Test Cost Reduction • DFT techniques are design efforts specifically employed to ensure that a device in testable. • Testers has to be engaged early in the product cycle • The product must be open for design changes to meet the testing requirements • In general, DFT is achieved by employing extra H/W. • Conflict between design engineers and test engineers. • Balanced between amount of DFT and gain achieved. 6 DrUshaMehta3December2019
- 7. 7 DrUshaMehta3December2019 Testing is complex, costly and time consuming Add extra hardware in a design to support testing. testing of design becomes easier Extra Hardware adds Extra power, delay and area Overall chip becomes costly, complex. Yield reduces Further, how to test the Design-for Test
- 8. DFT…… Advantages: • Fault coverage ↑ • Test generation (development) time ↓ • Test length (hopefully)↓ • Test Memory (hopefully)↓ • Test application time ↓ • Support a test hierarchy • Concurrent engineering • Reduce life-cycle costs In short Drawbacks: • Pin Overhead • Area / Yield • Performance degradation • Design Time ⇒There is no free lunch ! 8 DrUshaMehta3December 2019
- 9. DFT Methods • Digital DFT • Ad-hoc methods • Structured methods: • Scan • Partial Scan • Built-in self-test (BIST) • Boundary scan • Analog and Mixed Signal DFT • Analog test bus 9 DrUshaMehta3December 2019
- 10. Digital DFT Techniques • Ad hoc DFT Techniques • Test points • Initialization • Monostable multivibrators (one shot) • Oscillators and clocks • Counter / Shift registers • Partitioning large circuits • Logic redundancy • Break global feedback paths • And many more…….. • Structured DFT Techniques • Full scan. • Partial scan. • BIST • Boundary Scan 10 DrUshaMehta3December2019
- 11. Ad hoc DFT Techniques
- 12. • Good design practices which are learnt through experience. • Guidelines only. No clear/ firm rules. • Automation is not easily possible • Design reviews conducted by experts or design auditing tools. • Disadvantages of ad-hoc DFT methods: • Experts and tools not always available. • Test generation is often manual with no guarantee of high fault coverage. • Design iterations may be necessary. 12 DrUshaMehta3December2019
- 13. Test Point Insertion…. 13 DrUshaMehta3December 2019 Block 1 Block 2 Block 1 is not observable, Block 2 is not controllable Block 1 Block 2 OR CP1 Improving controllability: Block 1 Block 2 Normal working mode: CP1 = 0, CP2 = 1 Controlling Block 2 with 1: CP1 = 1, CP2 = 1 Controlling Block 2 with 0: CP2 = 0 MUX CP1 AND CP2 CP2 Normal working mode: CP2 = 0 Controlling Block 2 with 1: CP1 = 1, CP2 = 1 Controlling Block 2 with 0: CP1 = 0, CP2 = 1 Method of Test Points:
- 14. Example of Control Point Insertion 14 DrUshaMehta3December 2019
- 15. Test Point Insertion….. 15 DrUshaMehta3December 2019 C1 C2 M C3 CP2 CP1 OP CP3 CP4 . . . . . .
- 17. Examples of good candidates for control points: • control, address, and data bus lines on bus-structured designs • enable/hold inputs of microprocessors • enable and read/write inputs to memory devices • clock and preset/clear inputs to memory devices (flip-flops, counters, ...) • data select inputs to multiplexers and demultiplexers • control lines on tristate devices Examples of good candidates for observation points: • stem lines associated with signals having high fanout • global feedback paths • redundant signal lines • outputs of logic devices having many inputs (multiplexers, parity generators) • outputs from state devices (flip-flops, counters, shift registers) • address, control and data busses 17 DrUshaMehta3December2019
- 18. Initializing • For sequential circuits… • To bring them in known state • Design the circuits that are easily initializable • Asynchronous preset/Clear inputs to the flipflop 18 DrUshaMehta3December2019
- 19. Monostable Multivibrators and Clocks • Disable internal one shot, OSC and clocks • inserting CP and/or OP while disabling these devices 19 DrUshaMehta3December2019
- 20. Logical redundancy: 20 DrUshaMehta3December2019 Redundancy should be avoided: • If a redundant fault occurs, it may invalidate some test for nonredundant faults • Redundant faults cause difficulty in calculating fault coverage • Much test generation time can be spent in trying to generate a test for a redundant fault Redundancy intentionally added: • To eliminate hazards in combinational circuits • To achieve high reliability (using error detecting circuits) • Triple Modular Redundancy 1 & & & 1->0 1 0 1 0 1 1 Hazard control circuitry: Redundant AND-gate Fault 0 not testable 0
- 21. Partitioning of registers (counters): 21 DrUshaMehta3December 2019 C REG 1 REG 2 IN IN OUTOUT CL CL C REG 1 REG 2 IN IN OUT OUT CL CL && && CP: Tester Data CP: Data Inhibit CP: Clock Inhibit && CP: Tester Data CP: Data Inhibit OP 16 bit counter divided into two 8-bit counters: Instead of 216 = 65536 clocks, 2x28 = 512 clocks needed If tested in parallel, only 256 clocks needed
- 22. Partitioning for Testability • Testability is the function of its depth. Smaller ckts are easier to test • If large circuits are broken down to add CP and OP by adding some extra hardware like MUXs • MUXs isolates each segment and improve the testability 22 DrUshaMehta3December2019
- 23. Partitioning…. 23 DrUshaMehta3December2019 • MUXs are transparent during normal operation
- 25. 25 DrUshaMehta3December 2019 • Two 2-to-1 MUXs are added to allow the β partition to directly observable on Z2 ( s=0) or the α and γpartitioned to be controlled to z1 and z2 (S=1) • I is used to control the “off-path” input .
- 26. Pseudo-Exhaustive Method of Partitioning proposed by McCluskey 26 DrUshaMehta3December 2019
- 31. Global Feedback Path • Break the global feedback path 31 DrUshaMehta3December2019
- 32. Dos and Don’ts • Avoid asynchronous feedback • Avoid delay dependant logic • Avoid parallal drives • Avoid monostable and self resetting logic • Avoid gated clock • Avoid redundant logic • Avoid high fanin fanout combinations • Make flipflops initializable • Separate digital and analog circuits • Provide test controls to difficult to control signals • Buses can be useful and make life easier • Consider ATE requirements ( tristate etc.) 32 DrUshaMehta3December2019
- 33. Structured DFT Techniques Scan Chain –Scan Test
- 34. • For N input combination circuit, 2N input patterns. For N inputs, M registers, sequential circuit, 2(N+M) patterns. • Complexity of testing sequential circuits due to • feedback loops • placement of the circuit in a known state • high chance for hazard, essential hazard • Timing problems 34 DrUshaMehta3December2019
- 35. Difficulties in Sequential ATPGs • Poor initializability. • Poor controllability/observability of state variables. • Gate count, number of flip-flops, and sequential depth do not explain the problem. • Cycles are mainly responsible for complexity 35 DrUshaMehta3December2019
- 36. Structured DFT • Structured DFT involves adding extra logic and signals dedicated for test according to some procedure. • The circuit has two modes, normal and test mode. • The most commonly used structured methods are Scan and BIST. 36 DrUshaMehta3December2019
- 37. Scan Based Designs 37 DrUshaMehta3December 2019 • Scan proposed in ’73 by Williams and Angell. • Main idea is to obtain control and observability for FFs. • It reduces sequential TPG to combinational TPG. • Scan-path design is to reduce test generation complexity for circuit containing storage devices and feedback path with combinational logic • The philosophy is to divide & conquer with the purpose to : • Set any internal state easily • Observe any state through a distinguishing sequence
- 38. Scan System • Circuit is designed using pre-specified design rules. • Test structure (hardware) is added to the verified design: • Add a test control (TC) primary input. • Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. • Make input/output of each scan shift register controllable/observable from PI/PO. • Use combinational ATPG to obtain tests for all testable faults in the combinational logic. • Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. 38 DrUshaMehta3December2019
- 39. Different Forms of Scan Design • Full Serial Integrated Scan • Multiple Scan • Partial Scan • Isolated Serial Scan • NonSerial/Random Access Scan 39 DrUshaMehta3December2019
- 40. Full Serial Integrated Scan 40 DrUshaMehta3December 2019
- 41. Scan Design Rules • Only D-type master-slave FFs should be used. No JK, toggle FFs or other forms of asynchronous logic. • At least on PI must be available for test. As shown in previous circuit, the Scan-in and Scan-out pins can be multiplexed (only one additional MUX is needed at Scan-out). Therefore, the only required extra pin is Scan-Enable, SE (or Test Control, TC). • All FFs must be controlled from PIs. Simple circuit transformations can be used to change FFs whose Clk is"gated" by an internal logic signal. • Clocks must not feed data inputs of the FFs. A race condition can result in normal mode otherwise.This is generally considered good design practice anyway. 41 DrUshaMehta3December2019
- 43. Scan System 43 DrUshaMehta3December 2019 Combinational Circuit F/F F/F F/F Primary Outputs Primary Inputs SCAN INSCAN OUT MODE MUX
- 44. Full Serial Integrated Scan 3 December 2019 Dr Usha Mehta 44
- 45. Scan-Path Design Any sequential circuit may be modeled as: 45 DrUshaMehta3December2019
- 46. Multiplexed Data Flipflop • Setting TE = 1 • Shifting the test patterns from SI into the flip-flops • Setting TE = 0 and after a sufficient time for combinational logic to settle, checking the output values • Applying a clock signal CLK • Setting TE = 1 and shifting out the flip-flop contents via Q 46 DrUshaMehta3December2019
- 47. Scan Flip-Flop (SFF) 47 D TC SD CK Q Q MUX D flip-flop Master latch Slave latch CK TC Normal mode, D selected Scan mode, SD selected Master open Slave open t t Logic overhead DrUshaMehta3December2019
- 48. Level-sensitive Scan Design • The latch works with the 3 phases A, B and C • For normal operation, clocks B and C • For shift operation, clocks B and A • Two-port flip-flop works with two non- overlapping clocks L1 (b) L1 L2 C D A B SCAN-IN L2 DrUshaMehta3December2019
- 49. Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) 49 D SD MCK Q Q D flip-flop Master latch Slave latch t SCK TCK SCK MCK TCK Normal mode MCK TCK Scan mode Logic overhead DrUshaMehta3December2019
- 50. Two Port Dual Clock Flipflop • Sometimes it is useful to separate the normal clock from scan clock 50 DrUshaMehta3December2019
- 51. Multiplexed Data Shift Register latch • It is often desirable to insure race-free operation by employing a two-phase non- overlapping clock 51 DrUshaMehta3December2019
- 52. Scan Design Flow • Complete HDL Design using scan design rules • Synthesize logic using the selected ASIC library • Convert regular FFs to scan FFs • Use test synthesis program • Connects the scan flipflops in a serial chain and clocks • Use test synthesis program • Generate test patterns automatically 52 DrUshaMehta3December2019
- 53. Hierarchical Scan • Scan flip-flops are chained within subnetworks before chaining subnetworks. • Advantages: • Automatic scan insertion in netlist • Circuit hierarchy preserved – helps in debugging and design changes • Disadvantage: Non-optimum chip layout. 53 SFF1 SFF2 SFF3 SFF4 SFF3SFF1 SFF2SFF4 Scanin Scanout Scanin Scanout Hierarchical netlist Flat layout DrUshaMehta3December2019
- 54. ATPG Example: S5378 54 Original 2,781 179 0 0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 414 Full-scan 2,781 0 179 15.66% 4,603 214/228 99.1% 100.0% 5 s 585 105,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length DrUshaMehta3December2019
- 55. Automated Scan Design Behavior, RTL, and logic Design and verification Gate-level netlist Scan design rule audits Combinational ATPG Scan hardware insertion Chip layout: Scan- chain optimization, timing verification Scan sequence and test program generation Design and test data for manufacturing Rule violations Scan netlist Combinational vectors Scan chain order Mask dataTest program Develop DFT Develop test DrUshaMehta3December2019
- 56. Scan Overheads • IO pins: One pin necessary. • Area overhead: • Gate overhead = [4 nsff/(ng+10nff)] x 100% where ng = comb. gates; nff = flip-flops • More accurate estimate must consider scan wiring and layout area. • Performance overhead: • Multiplexer delay added in combinational path; approx. two gate-delays. • Flip-flop output loading due to one additional fanout; approx. 5 - 6%. 56 DrUshaMehta3December2019
- 57. Optimum Scan Layout 57 IO pad Flip- flop cell Interconnects Routing channels SFF cell TC SCANIN SCAN OUT Y X X’ Y’ Active areas: XY and X’Y’ DrUshaMehta3December2019
- 58. Tests for Scan Circuits Two phases: • Shift test • Set TC= 0, and shift toggle sequence 00110011... using Clk. • The length is nsff + 4, where nsff are the number of scan flops. • This sequence produces all 4 transitions, 0- >0, 0->1, 1->1 and 1->0,catches all/most SA faults. • The Shift test can be used in either single- clock or two-clock designs. • This creates a continuous path between SI and SO for application of 0 and 1. • Combinational logic test • This phase allows the combination logic circuit to be tested for SA faults. • An ATPG algorithm is used where outputs of Scan FFs are treated as pseudo-PIs (completely controllable) and inputs are treated as pseudo-POs. 58 DrUshaMehta3December2019
- 59. Scan Test Operation Loop • Put the chip into scan mode • Shift data into scan chain through Scan in • While scanning in the next pattern through Scan in, scanning out the results through Scan out of the previous pattern • Apply the functional clock to latch responses into scan FFs • Perform above 2 steps for each test pattern 59 DrUshaMehta3December2019
- 60. Scan Test Sequence • Each vector contains two parts: ix and sx represent PIs and pseudo-PIs (state variables), ox and nx represent POs and pseudo-POs (next state variables). • For given example, Faults at POs under 1st vector are detected after 10th Clk. • However, faults captured in FFs for this vector are detected on 11th through 19th Clk, during scanin of 2nd vector. 3 December 2019 Dr Usha Mehta 60
- 61. Test Time 61 DrUshaMehta3December2019 • The general formula for the length of the test (which includes Shift test) is: • For a circuit with 2,000 FFs and 500 vectors, 1,004,504 Clks needed.
- 62. Other Forms of Scan 62 DrUshaMehta3December 2019
- 63. Multiple Scan Chains and Partial Scan 63 DrUshaMehta3December2019
- 64. Multiple Scan Chains • Test application time is function of the numbers of ff scanned. • If more numbers of chain operated in parallel, test time reduces. • Instead of stringing all the flip-flops or the latches in one shift register • Partition them is several chains • Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. • Test sequence length is determined by the longest scan shift register. • Just one test control (TC) pin is essential. • The advantages are: • compatible with multiple clock designs • Shorten test application time • Simplify the stitching of the flip-flops • But, may require extra pins DrUshaMehta3December2019
- 65. Partial Scan Chain • To scan only a subset of the flip-flops • Objectives: The circuit is easier to test by the sequential ATPG. The area overhead is minimized. The placement of the flip-flops is such that the interconnects are minimized. The delays are shortened. • Retains many advantages of full scan and reduces the cost • Exclude certain flip-flops • Fault coverage is a function of the number of scan FFs • Main researches • Flip-flop selection • Test length reduction • Retiming • What do we lose in partial scan? • Loss of fault coverage • Difficult to automate in synthesis environments • Used in conjunction with other schemes 65 DrUshaMehta3December2019
- 66. How to select this subset? • It is an NP-complete problem • Heuristics on graph model to select the minimum feedback vertex set (MFVS) to transform the FSM into an acyclic graph • How to choose scan FFs and non-scan FFs? • Testability Analysis • Structural Analysis • ATPG Based Analysis • Used in conjunction with other schemes • Main researches • Flip-flop selection • Test length reduction DrUshaMehta3December2019
- 69. Random Access Scan • Treat each one of the latch elements as a bit in memory • Each bit in the memory has its own unique address, and it has a port which can load data into the latches so that the contents of the latch can be observed • There is only one scan-in and one scan-out • Addressing scheme which allows each latch to be uniquely selected, so that it can be either controlled or observed. • Normal operation • Scan clock is off • Only one latch receives the scan clock and that value is loaded into the latch. • High Area Overhead • Concept of crosscheck • Less Test Power 69 DrUshaMehta3December 2019
- 71. RAS Applications • Logic test: • reduced test length. • Delay test: • Easy to generate single-input-change (SIC) delay tests. • Advantage: • RAS may be suitable for certain architecture, e.g., where memory is implemented as a RAM block. • Disadvantages: • Not suitable for random logic architecture • High overhead – gates added to SFF, address decoder, address register, extra pins and routing DrUshaMehta3December2019
- 72. Advantages of Scan • Structured design is possible • Can use combinational ATPG • Significant reduction of test generation time • High fault coverage, typically 99.5 • Ease of fault diagnosis 72 DrUshaMehta3December2019
- 73. Disadvantage of Scan • Additional circuitry is added to FF • SCAN flip-flop is more expensive • Additional chip area • Additional circuit pins • Performance penalty • Increased propagation time • Test time increase • Due to shift in and shift out • Some designs are not easily realizable as scan designs • Need to store Patterns • Motivation for BIST • Inability to test circuits at full speed • Motivation for Delay Fault Testing 73 DrUshaMehta3December2019