Design of Efficient 4×4 Quaternary Vedic Multiplier Using Current-Mode Multi-Valued Logic

Int. J. on Recent Trends in Engineering and Technology, Vol. 10, No. 2, Jan 2014

Design of Efficient 4×4 Quaternary Vedic Multiplier
Using Current-Mode Multi-Valued Logic
Ashish S. Shende1, M. A. Gaikwad2, D. R. Dandekar3
P. G. Student, P. G. Department of Electronics Engineering, BDCOE, Wardha, India
Email: mr.ashishshende@gmail.com
2
Principal, BDCOE, Wardha, India, Email: gaikma@rediffmail.com
3
M.Tech. (Electronics) Co-ordinator, P. G. Department of Electronics Engineering, BDCOE, Wardha, India
Email: d.dandekar@rediffmail.com
1

Abstract— Vedic multiplier is based on ancient Indian Vedic mathematics that offers
simpler and hierarchical structure. Multi-valued logic results in the effective utilization of
interconnections, which reduces the chip size and delay. This paper proposes a new design
of 4×4 Vedic multiplier using quaternary current-mode multi-valued logic, equivalent to
iplier has
very low transistor-count and consumes very low power as compared to other multiplier
designs. Since the performance of a digital signal processor depends mainly on the
multipliers used, the proposed approach can greatly enhance the performance of a digital
signal processing system.
Index Terms— VLSI, current-mode multi-valued logic, quaternary signal, Vedic multiplier,
digital signal processing

I. INTRODUCTION
Multiplier is an essential component of a Digital Signal Processor (DSP). Multipliers are useful in
implementation of systems realizing many important functions such as fast Fourier transforms and multiplyaccumulate. Performance of a DSP depends heavily on its multipliers. Hence, a DSP chip needs compact,
fast, reliable and low power consuming multipliers. The delay in an arithmetic unit of DSP is mainly due to
its multipliers. Longer word-lengths in binary logic make the multiplier large and complex. In binary logic,
the size of the device is reduced by reducing the size of the transistor. But it has a limit, since the size of
transistor cannot be reduced indefinitely. By applying multi-valued logic to the multiplier design, wordlengths and the number of transistors can be greatly reduced. There are various multipliers for binary logic
such as Array multiplier, Booth multiplier, Wallace tree multiplier and Vedic multiplier. Vedic multiplier has
caught the attention of researchers in recent years because of its superiority over other multipliers. If the
functional blocks designed in multi-valued logic are used in Vedic multiplier’s architecture, it will surely
enhance the performance of multiplier and hence the whole DSP chip.
A. Vedic Mathematics
Sanskrit word ‘Veda’ means ‘Knowledge’. Vedic Mathematics is a name which is heard many times with
reference to the techniques for solving mathematical problems mentally. Vedic mathematics techniques were
DOI: 01.IJRTET.10.2.24
© Association of Computer Electronics and Electrical Engineers, 2013

rediscovered in the early twentieth century from ancient Indian sculptures by Sri Bharati Krishna Tirthaji
Maharaj. These methods can be directly applied to trigonometry, plain and spherical geometry, conics,
calculus and applied mathematics of various kinds.
Vedic mathematics is based on 16 sutras or formulae given in ancient Indian Vedas. Two of these sutras are
useful for multiplication, namely, Nikhilam sutra and Urdhva Tiryakbhyam sutra. Nikhilam sutra means “all
from 9 and last from 10”. It is more efficient when the operands are very large and close to an integer power
of 10. Its limitation is that both operands should be either less than or greater than the selected power of 10.
Urdhva Tiryakbhyam sutra, which means “vertically and crosswise”, is more popular than Nikhilam sutra
since it is applicable in all cases. Fig. 1 shows how the multiplication 96×93 can be done using Nikhilam
sutra and Fig. 2 illustrates the line diagram for multiplication of two 4-bit numbers using Urdhva
Tiryakbhyam sutra. It can be clearly visualized from these figures that Vedic multiplication is much simpler
than conventional multiplication.
Vedic method for multiplication strikes a difference in the actual process of multiplication itself. It enables
parallel generation of intermediate products and eliminates unwanted multiplication steps with zeros. This
reduces the number of adders required for designing a multiplier. Partial products are calculated in parallel
and delay associated is mainly the time taken by carry to propagate through the adders. Generation of all
partial products can be done with the concurrent addition of these partial products. It makes the multiplier
independent of clock frequency of processor, thereby reducing power dissipation, which avoids catastrophic
device failures. Vedic architecture gives chances for modular design where smaller block can be used to
design the bigger one. This helps in designing multiplier in VHDL, as it gives effective utilization of
structural method of modeling. Vedic multiplier requires less number of LUTs, which reduces the hardware
and memory requirement, thereby reducing the power consumption, without compromising delay. The speed,
power and area improvements are gained due to the hierarchical structuring and effective addition of partial
products. This enables large saving of resources when used in FPGA or ASIC for digital signal processing.
So, be it VLSI implementation or implementation using Hardware Description Language, employing Vedic
techniques reduces the complexity, execution time, chip area, power consumption and hardware cost [1]–[5].

Figure 1. Multiplication of Two Decimal Numbers by Nikhilam Sutra

Figure 2. Line Diagram for Multiplication of Two 4
bit Numbers Using Urdhva Tiryakbhyam Sutra

B. Multi-Valued Logic (MVL)
It was first proposed by Jan Lukasiewicz, Polish minister of Education in 1919, followed by Emil Post,
American logician born in Poland. MVL employs more than two discrete levels of a signal, such as ternary,
quaternary or even more.
Binary logic dominates the hardware implementation of DSP systems. But it has many drawbacks and
limitations. A signal cannot always be just ON or OFF, it can assume another state such as UNKNOWN,
DON'T CARE, HIGH IMPEDANCE, etc. Not considering these states can result in inefficient processing of
the data. Also, binary logic results in longer word-lengths which increase the number of interconnections and
hence the chip size. This hampers the performance of the system.
Researchers, who work in MVL, feel that the binary logic is already doomed. This is just like, if you have
colour pencils with you, why to draw a black and white picture! As the amount of information to be
60

processed goes on increasing, binary logic loses its dominance and MVL starts gaining its power. Though it
is possible to employ MVL in almost all the areas where binary logic is used, the main potential of MVL is
explored in fuzzy applications and arithmetic circuits.
C. Operating Modes of MVL
MVL can be employed in either voltage-mode or current-mode. In voltage-mode MVL, operating voltage
range is divided into the number of logical values to be represented, for example, for 5V circuit employing
quaternary logic, logic levels 0, 1, 2 and 3 can be assigned to 0V, 1.5V, 3V and 5V respectively. In currentmode MVL, currents are usually defined to have logical levels that are integer multiples of a reference
current unit, for example, logic levels 0, 1, 2 and 3 can be assigned to 0 A, 10 A, 20 A and 30 A
respectively. The voltage-mode MVL is preferred when the prime parameter to deal with is the power
dissipation. If we go on increasing the logic levels in the voltage mode, the problem of noise margin will get
worse. Hence, for higher radix, current-mode designs are preferred. The main advantage of current-mode is
that it reduces the number of active devices and wiring complexity since the frequently used linear sum
operation can be performed simply by connecting those wires together by Kirchhoff’s current law. Carry unit
is much simpler since carry-out signal will be assigned logic level 1 if the analog addition of inputs goes
beyond certain reference current.
D. Advantages of MVL over Binary Logic
The advantages of using MVL over binary logic are:
1) It reduces the number of interconnections.
2) It results in smaller circuitry, low power dissipation, greater speed and low cross-talk noise.
3) It increases the data processing capability per unit chip area.
4) Quaternary logic signals easily interface with the binary world; they may be decoded directly into their
two-digit binary equivalents.
5) It offers the use of signal space that combines some of the efficiency of analog signaling with the noise
immunity of digital signaling.
In spite of having so many advantages, there is less research interest in MVL because such circuits are not yet
widely used in industrial products. This is because the binary logic is simple and sufficient for present day
technologies. But as more complex technologies are being invented, the future will be of MVL and not
binary logic. The research in MVL is still in initial stage and the work is more theoretical and fundamental.
But if the hardware implementation of MVL circuits is popularized, MVL will surely dominate the binary
logic one day.
II. ARCHITECTURE OF PROPOSED QUATERNARY CURRENT-M ODE VEDIC MULTIPLIER
Fig. 3 and Fig. 4 show proposed 2×2 and 4×4 quaternary current-mode Vedic multipliers which are derived
from 2×2 and 4×4 binary Vedic multipliers given in Ref. [5]. From Fig. 4, it can be surely concluded that the
application of current-mode MVL reduces the number of adders in the multiplier architecture as the number
of bits to be processed goes on increasing. Furthermore, proposed 4×4 quaternary multiplier is equivalent to
8×8 binary multiplier, which shows great reduction in the circuitry because of MVL.

Figure 3(a). 2×2 Binary Vedic Multiplier

Figure 3(b).Proposed 2×2 Quaternary Current-mode Vedic Multiplier

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Figure 4(a). 4×4 Binary Vedic Multiplier

Figure 4(b). Proposed 4×4 Quaternary Current-mode
Vedic Multiplier

III. CIRCUIT-LEVEL DESIGNS OF BASIC BLOCKS USED
The basic current-mode building blocks used to perform most of the arithmetic operations are current
mirrors, current comparators and switched current sources. Using these basic blocks, various functional
blocks such as adders, subtractors, etc can be designed in current-mode. A current mirror is used to produce
multiple copies of an input current, each multiplied by a constant factor. It can also be used to change the
sign of current just by reversing the direction of its copy. Comparators are required so that we can restore a
current-mode signal to its proper signal level. A current comparator requires reference current to compare
against and is generally lumped with the switched current sources.
Fig. 5 shows the dual-rail comparator from Ref. [6]. ‘I0’ is the unit step current. Input current ‘X’ is
compared against four references, namely, 0.5I0, 1.5I0, 2.5I0 and 3.5I0. If the input current is greater than the
particular reference current, a voltage equal to VDD is produced at that comparator branch. Dual-rail structure
is useful for dealing with the signed numbers. But we are interested only in unsigned numbers. Hence we
have used the single-rail comparator, shown in Fig. 6. Input current is compared with three references, equal
to 0.5 times, 1.5 times and 2.5 times of the unit step current. If the input current is greater than the reference
current, VDD is generated at that comparator branch, which is then converted into GND voltage through the
CMOS inverter.
To design the current mirror, high-swing cascode current mirror (HCCM) topology is used. Fig. 7 shows
PMOS HCCM mirror from Ref. [7]. This mirror is suitable for low voltage applications.
Fig. 8 shows the partial product generator (PPG), consisting of a comparator and PMOS current mirror. The
numbers 0.5, 1.5 and 2.5 in comparator denote that the reference currents are 0.5 times, 1.5 times and 2.5
times of the unit step current, respectively. If input ‘b’ is greater than the reference current, comparator gives
0V at the particular output, which turns ON the subsequent PMOS, thereby passing a copy of input ‘a’. For
example, if b is at logic 2, then two PMOSes will be ON and the output will be ‘2a’ ,that is, ‘b×a’. In
quaternary number system the logical set is {0, 1, 2, 3}, hence the possible values of partial product are 0, 1,
2, 3, 4, 6 and 9. A quaternary full adder (QFA), shown in Fig. 9, is used to convert this partial product into
proper quaternary form in order to get the final product of 1×1 multiplier.
QFA consists of NP mirror, two threshold detectors and NMOS mirror. NP mirror is formed by connecting
single-output NMOS mirror with triple-output PMOS mirror. ‘TD (3.5;1;1)’ is a threshold detector. If its
input is greater than logic 3.5, it gives current equal to logic 1 at its both outputs. It is formed by connecting a
comparator with simple mirror structure, as shown in Fig. 10. HCCM topology is used to design the NMOS
62

mirror from Ref. [8] as shown in Fig. 11. The NMOS mirror connected after threshold detectors in QFA is
designed in such a way that it draws the current equal to four times of its input current. This can be done by
increasing W/L of ‘M3’ of NMOS mirror. NP mirror produces three copies of input current ‘in’. This input
current is compared with logic values 3.5 and 7.5 and accordingly the carry is set to 1 or 2, subtracting 4 or 8
respectively from the input current using NMOS mirror.
Fig. 3 shows that AND gate in 2×2 binary Vedic multiplier is replaced by actual 1×1 multiplier while
designing proposed 2×2 quaternary Vedic multiplier. By connecting QFA with PPG, a quaternary 1×1
multiplier can be formed in current-mode.

Figure 5. Schematic of Dual-Rail MVCM Comparator from Ref. [6]

Figure 6. Single-Rail Comparator Used in Proposed Design

Figure 7. PMOS HCCM Mirror from Ref. [7]

63

Figure 8. Partial Product Generator (PPG)

Figure 9. Quaternary Full Adder (QFA)

Figure 10. Threshold Detector With Reference of Logic 3.5

Figure 11. NMOS HCCM Mirror from Ref. [8]

As shown in Fig. 3(b), full adder (FA) is required alongwith
64

1×1 multipliers to design proposed 2×2

quaternary multiplier. FA is designed in similar way to QFA but with some modifications. Since QFA is
attached to PPG, its maximum possible input is logic 9. But FA is simple quaternary adder and hence its
maximum possible input is logic 7. Hence, while designing FA, threshold detector with reference 7.5 is not
needed. For designing FA, we are using the topology such that instead of considering each of its inputs
individually, linear sum of all inputs is considered as single input of FA. Hence, FA may have three or more
inputs but, at any instance, the linear sum of all inputs should not be greater than logic 7.
Ripple carry adder structure is used to design 4-digit adder required for designing proposed 4×4 quaternary
multiplier.
IV. SIMULATION RESULTS AND ANALYSIS
with the power supply of 1V. The current step i
multipliers. The outputs are calculated by allowing the error of ±10% of current step, tha
shows that proposed multiplier has very low transistor-count as compared to other multipliers in the
literature.
Generally, propagation delay is measured between 50% of input transition and corresponding 50% of output
transition. But this definition is suitable only for binary circuits. For MVL circuits, this definition is not
acceptable since the linearity in the output is not like binary circuits due to more than two logic levels. No
standard definition of propagation delay has been found in the available literature. Hence, own definition of
propagation delay is used for the analysis purpose. The definition used for calculating the propagation delay
is as follows:
“The time required for the output to reach a value equal to
(Final value of output) ± (10% of unit step current)
after the input becomes stable, is the propagation delay”.
The definition of propagation delay used in the paper can be better understood from the graph shown in Fig.
12. Yellow colored line shows the input and gr
±10% of unit step current in the final value of output. Since the unit step current used in the proposed design
at 529.10ns. Thus the propagation delay can be calculated as 529.10ns–520ns = 9.10ns.
Since own definition of propagation delay is used, large number of readings are taken and are analyzed in
detail. In binary logic, a digit can change only in two ways, 0
can change in 12 different ways. The possible variations in quaternary digit’s value are 0
1
possible ways and delays are calculated at all the outputs which undergo the change.
First, A3 is varied in all 12 ways for the combination ‘A3320×3032’ and the delays are calculated at the
outputs. Table II shows all the values of delay and power consumption calculated for variations in A3. ‘Di’
denotes the delay at ith digit. Power consumption is also found for each combination. ‘-’ denotes that the
output digit does not undergo any change for that variation in input digit.
Then, A2 is varied in all the 12 ways for the combination ‘2A231×1302’ and the delays are calculated at the
outputs. Power consumption is also found for each combination. Table III shows all the values of delay and
power consumption calculated for variations in A2.
Then, A1 is varied in all the 12 ways for the combination ‘12A 12×2013’ and the delays are calculated at the
outputs. Power consumption is also found for each combination. Table IV shows all the values of delay and
Finally, A0 is varied in all the 12 ways for the combination ‘023A 0×2301’ and the delays are calculated at the
outputs. Power consumption is also found for each combination. Table V shows all the values of delay and
Thus, total 206 readings are taken for propagation delay and 48 readings are taken for the power
consumption. Complete analysis of propagation delay and power consumption is shown in Table VI. The
analysis in Table VI shows that the proposed multiplier has very low power consumption but larger delay. It
also shows that the readings of delay are spread over a wide range. But the power consumption of proposed
multiplier is confined to a very small range. Also, the average of best-case and worst-case power
consumptions is approximately equal to the average of all readings of power consumption. Table VII shows
65

the comparison of average power consumption of proposed multiplier with some other multipliers in the
literature. It shows that the proposed multiplier is excellent in terms of power consumption.
TABLE I. COMPARISON OF TRANSISTOR-COUNT
Year
Proposed
Ref. [9]
Ref. [10]
Ref. [11]

2006
2011
2008

Ref. [12]

2009

Ref. [13]

2011

Transistor Count
1271
2544
2510
1648
2292 (CMOS)
2120 (CPL)
2920 (Hybrid)
1952

% Reduction
50.03%
49.36%
22.87%
44.54%
40.04%
56.47%
34.88%

Figure 12. Graph Showing Propagation Delay
TABLE II. DELAY AND POWER CONSUMPTION OF PROPOSED M ULTIPLIER FOR VARYING A3
Variation

Propagation Delay (ns)

Power
Consumption (mW)

0

D7
78.58

D6
-

D5
82.74

D4
82.27

D3
131.70

D2
-

D1
-

D0
-

0
0
1

68.73
88.60
27.75

113.79
94.76
83.68

122.09
72.49
92.68

122.12
112.21
-

94.68
63.34

-

-

-

0.69
0.70
0.67

1
2
3

48.41
23.18
29.16

47.77
36.66
77.95

47.46
-

55.36
84.66
54.41

75.45
49.13

-

-

-

0.68
0.69
0.68

3
3

48.33
47.04

91.99
90.47

48.33
74.20

43.32
86.99

37.69

-

-

-

0.67
0.70

2

38.12

80.65

52.76

-

96.98

-

-

-

0.66

2
1

34.37
31.84

78.04
-

98.90
58.46

97.07
74.56

62.73

-

-

-

0.69
0.68

66

0.68

TABLE III. DELAY AND POWER CONSUMPTION OF PROPOSED MULTIPLIER FOR VARYING A2
Variation


Power
Consumption (mW)

0
0

D7
69.78
57.61

D6
82.41
51.26

D5
76.67
-

D4
129.50
71.22

D3
49.90

D2
91.60
-

D1
-

D0
-

0
1

47.50
-

83.65
-

66.34
55.90

62.08
-

39.91
34.92

67.55
57.29

-

-

0.57
0.53

1
2
3

-

49.03
31.80
43.41

37.87
38.17

62.29
45.06
73.12

40.49
-

40.34
50.75

-

-

0.54
0.54
0.54

3
3
2

51.35
-

99.14
76.07
-

51.73
74.74

51.03
50.60
-

45.23
78.69
88.35

72.32
52.97

-

-

0.54
0.56
0.53

2
1

48.12
85.20

72.59
87.36

76.27

55.06
36.85

67.29
-

82.74

-

-

0.55
0.55

0.55
0.56

TABLE IV. DELAY AND P OWER CONSUMPTION OF PROPOSED MULTIPLIER FOR VARYING A1
Variation


Power
Consumption (mW)

0

D7
-

D6
-

D5
94.24

D4
109.76

D3
90.95

D2
116.34

D1
89.54

D0
-

0
0
1

-

-

104.07
74.32
-

174.77
114.54

141.47
77.26
-

99.54
50.17

73.34
73.48
39.91

-

0.53
0.54
0.50

1
2

-

-

50.38
30.74

151.40
85.40

21.94
40.49

24.24

16.42
45.51

-

0.52
0.52

3
3
3

-

-

41.33
34.99
124.47

65.97
73.57
103.91

70.95
54.13
48.56

24.02
49.35

25.60
51.70
77.42

-

0.52
0.52
0.54

2
2
1

-

-

115.77
134.87

96.78
109.93

47.38
55.42

44.18
63.74

50.42
73.75
74.36

-

0.50
0.52
0.52

0.53

TABLE V. DELAY A ND P OWER CONSUMPTION OF PROPOSED MULTIPLIER FOR VARYING A0
Variation

D4
D3
D2

D1

D0

Power
Consumption (mW)

118.08
51.97
104.87

-

90.49
50.64
48.88

0.61
0.62
0.63

84.23
49.18
101.79

31.79
62.06
60.17

-

17.48
17.69
18.65

0.59
0.61
0.61

38.84
55.12

66.69
54.04

29.96
81.19

-

16.72
17.94

0.61
0.60

56.61
-

31.95
22.06

46.76
54.82

77.72
56.20
94.37

-

44.47
19.01
43.64

0.63
0.59
0.61

-

49.87

53.06

64.73

-

43.51

0.61

D7

D6

D5

0
0
0

-

46.95

56.60

89.43
124.99
50.81

76.69
127.67
-

1
1
2

-

16.56
22.72

24.84
31.46

20.55
27.30

3
3

-

57.81
46.07

71.53
57.66

3
2
2

-

40.17
-

1

-

-

67

TABLE VI. ANALYSIS OF DELAY AND POWER CONSUMPTION OF PROPOSED MULTIPLIER
Sr. No.

Parameter

Value

1.
2.
3.

Best-case Delay (ns)
Worst-case Delay (ns)
Difference Between Best-case and Worst-case Delays (ns)

16.42
174.77
158.35

4.
5.

Average of Best-case and Worst-case Delays (ns)
Average of All Readings of Delay (ns)

95.59
64.63

6.
7.
8.

Average of Best 30 Readings of Delay (ns)
Average of Worst 30 Readings of Delay (ns)
Best-case Power Consumption (mW)

25.25
116.44
0.50

9.
10.
11.

Worst-case Power Consumption (mW)
Difference Between Best-case and Worst-case Power Consumptions (mW)
Average of Best-case and Worst-case Power Consumptions (mW)

0.70
0.20
0.60

12.
13.

Average of All Readings of Power Consumption (mW)
Power Consumption for Best-case Delay (mW)

0.59
0.52

14.

Power Consumption for Worst-case Delay (mW)

0.54

TABLE VII. COMPARISON OF POWER CONSUMPTION
Proposed

Ref. [9]
2006

Ref. [10]
2011

Ref. [14]
2005

Ref. [15]
2005

Ref. [16]
2006

Ref. [17]
2007

1
0.18
0.59

3.3
0.35
4.86

1.8
0.18
10

1.8
0.18
22.4

1.8
0.18
1.416

1.2
0.13
6.38

0.18
19

87.86%

94.10%

97.36%

58.33%

90.75%

96.89%

Year
Supply Voltage (V)
Power Consumption (mW)
% Reduction

V. CONCLUSIONS
Since the research work done in multi-valued logic is in fundamental stage, there is no standard circuitry
established. Different researchers apply different logics. Thus there is a lot of scope to apply our own
thinking and logics. This paper shows that the circuits designed in current-mode multi-valued logic, when
implemented with Vedic architecture, yield a better multiplier design. Proposed multiplier is found to be
superior to some previously designed multipliers in the literature in terms of transistor-count and power
consumption. This multiplier consists of many smaller blocks such as current mirrors, current comparators
and threshold detectors, where the output of one block is given as input to the next block. Thus, every block
has to wait for the results of previous block. This increases delay of the multiplier. Delay of the proposed
multiplier can be reduced by using some larger blocks for designing partial product generator and quaternary
adders. This will be the focus of our future work.
VI. ACKNOWLEDGMENT
The authors want to thank Mr. Rehan Maroofi, First Impression Technologies, Nagpur, India, for his support
in carrying out the simulations successfully.
REFERENCES
[1] A. Kanhe, S. K. Das and A. K. Singh, “Design and implementation of floating point multiplier based on Vedic
multiplication technique”, IEEE International Conference on Communication, Information & Computing
Technology, pp. 1–4, 2012
[2] L. Sriraman and T. Prabakar, “Design and implementation of two variable multiplier using KCM and Vedic
mathematics”, IEEE International Conference on Recent Advances in Information Technology, pp. 782–787, 2012
[3] Ashish Shende, M. A. Gaikwad and D. R. Dandekar, “Application of current-mode multi-valued logic in the design of
Vedic multiplier”, International Journal of Computer Applications, pp. 13–16, March 2013

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[4] K. S. Gurumurthy and M. S. Prahalad, “Fast and power efficient 16×16 array of array multiplier using Vedic
multiplication”, IEEE International Microsystems Packaging Assembly and Circuits Technology Conference, pp. 1–
4, 2010
[5] Sumit R. Vaidya, “Design of high performance 8×8-bit multiplier based on Vedic mathematics in ASIC”, Dissertation
for M.Tech. (Electronics), BDCOE, RTM Nagpur University, India, January 2011
[6] T. Ike, T. Hanyu and M. Kameyama, “Dual-rail multiple-valued current-mode VLSI with biasing current sources”,
Proc. 31st IEEE International Symposium on Multiple-Valued Logic, no. 31, pp. 21–26, Poland, May 2001
[7] X. Zhang and E. I. El-Masry, “A regulated body-driven CMOS current mirror for low-voltage applications”, IEEE
Transactions on Circuits And Systems, Express Briefs, vol. 51, no. 10, October 2004
[8] J. Ramirez-Angulo, S. R. S. Garimella, A. J. Lopez-Martin and R. G. Carvajal, “Gain programmable current mirrors
based on current steering”, Electronics Letters, vol. 42, no. 10, May 2006
[9] L. Y. Sang and K. J. Beom, “Design of a low-power 8×8-bit parallel multiplier using MOS current mode logic
circuit”, IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1502–1504, 2006
[10] D. Yavuz and Y. Tulay, “High performance 8-bit MUX based multiplier design using MOS current mode logic”,
IEEE International Conference on Electrical and Electronics Engineering, pp. II-89–II-93, 2011
[11] Agarwal S., Pavankumar V. K. and Yokesh R., “Energy-efficient, high performance circuits for arithmetic units”,
IEEE International Conference on VLSI Design, pp. 371–376, 2008
[12] Ramanthan P., Vanathi P. T., Chaubey A. and Senthilraja N., “Decomposition algorithm for power delay product
optimization in Wallace multiplier”, IEEE International Conference on Control, Automation, Communication and
Energy Conservation, pp. 1–6, 2009
[13] Tang A. J. J. and Reyes J. A., “Comparative analysis of low power multiplier architectures”, IEEE Fifth Asia
Modeling Symposium, pp. 270–274, 2011
[14] A. Khatibzadeh, A. Raahemifar and M. Ahmadi, “A 1.8V 1.1GHz novel digital multiplier”, Proc. IEEE Canadian
Conf. on Electrical and Computer Engineering, pp. 686–689, 2005
[15] Rizwan Mudassir and Z. Abid, “New parallel multipliers based on low power adders”, IEEE Canadian Conf. on
Eletrical and Computer Engineering, Saskatoon, pp. 694–697, May 2005
[16] J. Y. Kang and J. L. Gaudiot, “A simple high-speed multiplier design”, IEEE Trans. on Computers, vol. 55, pp.
1253–1257, 2006
[17] Mirhassani Mitra, Ahmadi Majid A., Jullien Graham A., “Digital multiplication using continuous valued digits”,
IEEE International Symposium on Circuits and Systems, pp. 3263–3266, 2007

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