![How can i know if my code is synthesizable [verilog]?
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Structural verilog typically means you are creating
description close to a netlist and the constructs you would
use in this case are a small subset of those that are
synthesizable.
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Structural , Behaviour are non-synthesizable
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However, these two model can simulate........???
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Behaviour Models : Higher level of modelling where
behaviour of logic is modelled
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RTL Models : Logic is modelled at register level
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Structural Models : Logic is modelled at both register level
and gate level.
11](https://image.slidesharecdn.com/85252544-fd30-4033-bb80-cff368389d6e-151015205653-lva1-app6891/85/2nd-presantation-11-320.jpg)
2nd presantation
- 1. Click to add Title Simulation vs Synthesis Synthesizable and Non-Synthesizable Construct Jatin Adroja Keval Vaishnav Nilesh Ramani e-Infochips Institute of Training Research and Academics Limited
- 2. 2 Outlines Introduction to Simulation & Synthesis 1 Simulation vs Synthesis 2 Sinthesizable Construct in Verilog 3 Non-Synthesizable Construct in verilog 4
- 3. Introduction to Simulation ● What is simulation? Process of creating models to that mimic the behaviour of the device ● Why Simulation is required? To verify the code & gate level design 3
- 4. Introduction to Synthesis ● What is synthesis? Process of converting high level description of design into an optimized gate-level representation. ● Why Synthesis is required? To convert RTL code into gate level design 4
- 5. Simulation vs Synthesis There are two kinds of simulation 1- behavioural (functional) simulation which is done pre- synthesis 2- Timing simulation which is done post-synthesis to ensure that it has achieved the required timing. 5 Pre-Synthesis Simulation Synthesis Post-Synthesis Simulation
- 6. Simulation vs Synthesis 6 RTL Design Code Synthesis = Translation + Optimization + Technology Mapping Generic Boolean (No timing Info) Translate (HDL Compiler) Target Device (Timing Info) Optimize+Mapping (HDL Compiler)
- 7. Simulation vs Synthesis ● Translation RTL to gate-level net-lists ● Optimization: Technology-independent logic-level optimization to reduce hardware for required functionality. ● Technology Mapping: Technology-independent net-lists are transformed into technology-dependent ones. 7
- 8. Simulation vs Synthesis Outputs 8 Synthesis Schematics Net-lists Reports Pre-Synthesis Simulation Post-Synthesis Simulation Functionality Check Functionality Check with Timing Info
- 9. What is Synthesizable? ● Combine things to make a whole... ● Ex. You read many books and combine them all the information into the one report. ● Ex. Electronic keyboard produce the sound of drum and violin this is example of a case where the keyboard synthesize the instruments. 9
- 10. Synthesizable ● Verilog allows several ways to describe one thing, Synthesis tools often require only a limited subset of constructs; ● Example: R ● Registers and Flip Flops must be described in a certain way 10
- 11. How can i know if my code is synthesizable [verilog]? ● Structural verilog typically means you are creating description close to a netlist and the constructs you would use in this case are a small subset of those that are synthesizable. ● Structural , Behaviour are non-synthesizable ● However, these two model can simulate........??? ● Behaviour Models : Higher level of modelling where behaviour of logic is modelled ● RTL Models : Logic is modelled at register level ● Structural Models : Logic is modelled at both register level and gate level. 11
- 12. Construct Supported in Synthesis 12 no Construct Type Keyword or Description note 1 ports Input,inout,output Input only IO level 2 parameters parameter This makes design more generic 3 module definition module 4 signals and variables wire, reg, tri Vectors are allowed 5 instantiation module instances / primitive gate instances E.g.- nand (out,a,b), bad idea to code RTL this way. 6 function and tasks function , task Timing constructs ignored
- 13. Construct Supported in Synthesis 13 no Construct Type Keyword or Description note 7 procedural always, if, else, case, casex, casez initial is not supported 8 procedural blocks begin, end, named blocks, disable Disabling of named blocks allowed 9 data flow assign Delay information is ignored 10 named Blocks disable Disabling of named block supported. 11 loops for, while, forever While and forever loops must contain @(posedge clk) or @(negedge clk)
- 14. Construct not Supported in Synthesis 14 Construct Type Notes initial Used only in test benches. events Events make more sense for syncing test bench components. real Real data type not supported. time Time data type not supported. force and release Force and release of data types not supported. fork join Use non-blocking assignments to get same effect. primitives Only gate level primitives are supported. table UDP and tables are not supported.
- 15. Non Synthesizable verilog Construct ● The verilog code which contains non-synthesizable elements can be defined as non synthesizable verilog constructs. 15
- 16. Non Synthesizable element ● Basic :– System tasks :- $display $random $monitor real constants :- floating point numbers, ● Data-types :– Real :- ::= real < list of reg >, floating point operations, Time :- Time quantities in i.e. $time Event :- wait event ● Modual instances :– Delay on built in gate 16
- 17. Non Synthesizable element ● Primitives :– UDPs, pullup, pulldown, pmos, nmos, cmos, rpmos, etc ● Reduction Operations :- '===' :- concider 'x' and 'z' values ' !== ' :- notconcider 'x' and 'z' values % :- module, / :- division ● Event control :- Event trigger ( -> ), Delay and wait ( # ) 17
- 18. Non Synthesizable element ● Continuous assignments :- using delay :- delay is not synthesizable. ● Procedural blocks :- initial :- start execution at time zero. ● Procedural statements :- fork – join :- parallel execution cause RASE condition. ● Procedural assignments :- assign – deassign :- used to model in combinational logic. 18
- 20. Questions?
- 21. Thank you