A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC platform for Embedded Applications

ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 02, August 2011

A PIC compatible RISC CPU core Implementation for
FPGA based Configurable SOC platform for
Embedded Applications
Haritha Madasi 1, S Nagakishore Bhavanam 2, Vaujadevi Midasala 3
1
Holy Mary Institute of Technology & Science, E.C.E Dept., Hyderabad, India
Email: harikha_bujji@yahoo.com
2
Guru Nanak Institute of Science & Technology, E.C.E Dept., Hyderabad, India
Email: kishorereddy.vlsi@gmail.com
3
Keshav Memorial Institute of Technology, E.C.E Dept., Hyderabad, India
Email: vasujadevi@gmail.com

Abstract—Modern embedded systems are built around the soft are pin and code compatible across the portfolio. PIC
core processors implemented on FPGA. The FPGAs being microcontrollers with XLP technology feature the world’s
capable of implementing custom hardware blocks giving the lowest active and sleep power consumption with flexible
advantage of ASICs, and allowing the implementation of power modes and wake-up sources.MPLAB® Integrate
processor platform are resulting in powerful Configurable-
development Environ-ment supports all PIC microcontrollers
system on chip(C-SoC)platforms. The Microchip’s PIC
microcontroller is very widely used microcontroller
with C Compiler support and common development boards.
architecture across various embedded systems. The Peripheral integration is key with communication and control
implementation of such core on FPGA is very much useful in peripherals like SPI, I2C™, UART, PWM, ADC and comparators as
CSOC based embedded systems. This type of designs can be well as specialized peripherals for USB, mTouch™ Sensing,
widely used in those controlling fields demanding low power LCD, CAN and Ethernet. Customers have made PIC MCUs a
consumption and high ratio of performance to price. In this worldwide standard, with over one million development
project a reduced instruction set computer (RISC) CPU IP systems shipped. PIC microcontrollers are quick and easy
core whose instructions are compatible with the Microchip to design into a wide variety of applications with a long history
PIC16C6Xseries of microcontrollers is implemented in VHDL.
of dependable product delivery[1].
The core is based on 8-bit RISC architecture and top-Down
design methodology is used in developing the core. The RISC
CPU core is based on Harvard architecture with 14-bit II. INTRODUCTION TO PIC 16X MICROCONTROLLER
instruction length and 8-bit data length and two-stage
The PIC16C63A/65B/73B/74B devices are low-cost,
instruction pipeline. The architecture will be designed aiming
at single cycle execution of the instructions, except those high-performance, CMOS, fully-static, 8 bit microcontrollers
related to program branches. Since this type of CPU based on in the PIC16CXX mid-range family.All PICmicro ®
RISC architecture, there are only 35 reduced instructions in microcontrollers employ an advanced RISC architecture[2].
its instruction set, which are easy to be learned and used. The The PIC16CXX microcontroller family has enhanced core
performance of the 8-bit RISC CPU is better than those of features, eight-level deep stack and multiple internal and
CPUs which are based on CISC architecture. Modelsim Xilinx external interrupt sources. The separate instruction and
Edition (MXE) will be used simulation and functional data buses of the Harvard architecture allow a 14-bit wide
verification. The Xilinx Spartan-3E FPGAs will be used instruction word with the separate 8-bit wide data. The two
synthesis and timing analysis. The results will be verified on
stage instruction pipeline allows all instructions to execute
chip with chipscope tool.
in a single cycle, except for program branches, which require
Keywords- CPU; RISC; IP Core; IC; MXE; Xilix. two cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
I. PIC MICROCONTROLLERS some of the architectural innovations used to achieve a very
high performance[1]. The PIC16C63A/73B devices have 22
PIC microcontrollers are finding their way into new I/O pins. The PIC16C65B/74B devices have 33 I/O pins.
applications like smart phones, audio accessories, video Each device has 192 bytes of RAM. In addition, several
gaming peripherals and advanced medical devices. peripheral features are available including: three timer/
Microchip provides solutions for the entire performance counters, two Capture/Compare/PWM modules and two
range of 8-bit microcontrollers, with easy-to-use development serial ports. The Synchronous Serial Port (SSP) can be
tools, complete technical documentation and post design- configured as either a 3-wire Serial Peripheral Interface (SPI)
in support through a global sales and distribution network. or the two-wire Inter-Integrated Circuit(I2C) bus. The
There are hundreds of 8-bit PIC microcontrollers to choose Un i ver sa l Synch ron ous Asyn ch r onous Receiver
from ranging from 6 to 100 pins and up to 128 KB Flash that Transmitter (USART) is also known as the Serial
Communications Interface or SCI. Also, a 5- channel high-
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DOI: 01.IJEPE.02.02. 44


speed 8-bit A/D is provided on the PIC16C73B, while As figure 3-1 show, the CPU module contains the datapath
the PIC16C74B offers 8 channels. The 8-bit resolution is and controller modules while the program store is external to
ideally suited for applications requiring low-cost analog the CPU Core. This means that the Program Store can be
interface, e.g., thermostat control, pressure sensing, etc. located off-chip if needed. Locating the Program Store on-
The PIC16C63A/65B/73B/74B devices have special chip however enables the CPU Core to execute at the internal
features to reduce external components, thus reducing cost, clock speed of CPU.
en ha n ci ng system rel ia bil i ty an d r educi n g power
consumption. There are four oscillator options, of which
the single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for high speed crystals. The
SLEEP (power-down) feature provides a power-saving mode.
The user can wake up the chip from SLEEP through several
external and internal interrupts and resets. A highly reliable
Watchdog Timer (WDT), with its own on-chip RC oscillator,
provides protection against soft- ware lock-up, and also
provides one way of waking the device from SLEEP. A UV
erasable CERDIP packaged version is ideal for code
devel opmen t , whi l e t he cost-effect ive On e-Ti me-
Programmable (OTP) version is suitable for production in any
volume. The PIC16C63A/65B/73B/74B devices fit nicely in
many applications ranging from security and remote sensors
to appliance control and automotive[1]. The EPROM
technology makes customization of application programs
(transmitter codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint packages
Figure 3-2. CPU architecture
make this microcontroller series perfect for all applications with
Figure 3-2 shows the CPU architectural overview. To begin
space limitations. Low cost, low power, high performance, ease
with, the CPU uses Harvard architecture, in which, program
of use and I/O flexibility make the PIC16C63A/65B/73B/74B
and data are accessed from separate memories using separate
devices very versatile, even in areas where no microcontroller
buses. This improves bandwidth over traditional von eumann
use has been considered before (e.g., timer functions, serial
architecture where program and data may be fetched from
communication, capture and compare, PWM functions and
the same memory using the same bus. Separating program
coprocessor applications)[3].
and data busses further allows instructions to be sized
differently than 8-bit wide data words. Instruction words are
III. RISC IP DESIGN
14-bits wide making it possible to have all single word
The CPU IP Core is an instruction-compatible of the instructions. A 14-bit wide program memory access bus
Microchip PIC16C6X -series microcontrollers. The CPU fetches a 14-bit instruction in a single cycle. A two-stage
having 22bit I/O ports only has 35 instructions which make pipeline overlaps fetch and execution of instructions.
the final hardware implementation compact. The CPU can Consequently, all instructions execute in a single cycle except
address up to 2048 instruction words. And we use two level for program branches. The CPU can directly or indirectly
pipe-line structures to improve the executing speed. Figure address its register files or data memory. All special function
3-1 below shows the main modules of the RISC CPU IP registers (including the program counter) are mapped in the
Core[2]. data memory. The CPU has a symmetrical instruction set that
makes it possible to carry out any operation on any register
using any addressing mode. This symmetrical nature makes
programming with the CPU simple yet efficient, thus
significantly reducing the learning curve. The CPU contains
an 8-bit ALU and working register (W). The ALU is a general
arithmetic unit. It performs arithmetic and Boolean functions
between data in the working register and any register file. The
ALU is 8-bits wide and capable of addition, subtraction, shift,
and logical operations. Unless otherwise mentioned, arithmetic
operations are two’s complement in nature. In two-operand
instructions, typically one operand is the working register (W
register), the other operand is a file register or an immediate
Figure 3-1. Main modules of RISC CPU IP Core constant. In single operand instructions, the operand is either
the working register or a file register.

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instruction word while an indirect address is taken from the
FSR Special Function Register. The address generation logic
is shown below in figure3-5.

Figure 3-3. Simplified datapath
Figure 3-3 shows a somewhat simplified datapath
architecture where the eight Special Function Registers are
not shown. This datapath is sufficient to execute most
instructions so it will be used to introduce the overall CPU IP
Core architecture.Most instructions in the datapath Figure 3-5. Direct and indirect address selection
architecture operate on either the ‘W’ or one of the ‘f’ As can be seen in Figure 3-5, the Register Address
registers. The ‘W’ register is input as the ALU’s first operand Multiplexer passes through either the ‘fffffff’ field in the
while the currently addressed ‘f’ register is input as the instruction word (bits 6:0) or the value in the SFR register.
second ALU operand. The ALU result is output on ‘alu_bus’ The ‘reg_addr_mux_sel’ signal determines which source bus
from where it is loaded into either the ‘W’ register or into the to route to ‘reg_addr_bus’. The CPU architecture has an
currently addressed ‘f’ register. The Controller either asserts eight-level stack that enables subroutines to be called via
the ‘load_w_reg’ or the ‘load_ram_reg’ depending on if the the CALL/RETLW instruction pair. Jumps to an absolute
instruction word in the instruction Register directs the result address can also be done via the GOTO instruction. Figure 3-
to the ‘W’ or ‘f’ register respectively [4]. In order for the ALU 6 below shows the Program Counter Datapath required to
to be able to update the STATUS register bits Z, C, and DC a allow the CALL, RETLW and GOTO instructions to be
separate ‘status_bus’ exists together with three control implemented.
signals named ‘load_z’, ‘load_d’ and ‘load_dc’. These signals
are displayed below in figure 4. Also note that figure 4
contains the ‘ALU Mux’ on operand input two which allows
the Controller to select the second ALU operand to come
from either the RAM Registers (shown above in figure 3) or
from one of the eight SFR (Special Function Register)
Registers [0..7]. The ALU knows from the ‘ir_reg_bus’ which
instruction word is currently being executed. The ‘carry_bit’
input is connected to the C bit in the STATUS register. This
is used during additions and subtractions. The
‘ram_data_bus’ input to the ALU Mux comes from the RAM
registers as shown above in figure 3-4. The ‘sfr_data_bus’
comes from the currently addressed SFR register.
Figure 3-6. Program counter and stack
As Figure 3-6 shows, the ‘pc_mux_sel’ input selects the
source of the data on the ‘pc_mux_bus’. The ‘pc_ register’
register is loaded on the rising edge of the clock signal when
the ‘load_pc_reg’ signal is asserted. The ‘inc_pc’ signal is
used to increment the Program Counter as each instruction is
executed. The ‘inc_stack’ and ‘dec_stack’ signals are used
to select which stack register will be loaded when the
‘load_stack’ signal is asserted. The ‘stack_bus’ always
outputs the data in the current stack location (i.e. the data
previously written to the stack location)[5]. The CPU IP Core
contains two bidirectional 8-bit I/O and a bidirectional 6-bit I/
O ports .The I/O port bits can individually be programmed as
input or output via the TRIS instruction. The output data (for
Figure 3-4. Datapath surrounding ALU
output ports) is programmed into GPIO registers. Figure 3-7
The CPU architecture allows both direct and indirect below shows the internal architecture of the ‘tri_state_port’
addresses. A direct address is encoded directly in the 14-bit module.
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Figure 3-7. I/O port logic
As can be seen in figure 3-7, the ‘alu_bus’ input allows
the TRIS and GPIO 8-bit registers to be loaded from ‘alu_bus’.
A TRIS registers is loaded from ‘alu_bus’ when a TRIS Figure 4-1. Simulation waveforms
instruction is executed. A GPIO register is loaded when Special Figure 4-2 shows instruction decoder waveforms.
Function Registers is the write target of an instruction [7] Instruction decoding happens based on the instruction format
(i.e. MOVWF). Setting a bit in the TRIS register puts the described in Chapter 2. MSB 2-bits indicate whether the
corresponding output driver in a hi-impedance mode. Clearing instruction is byte oriented or bit oriented or control
a bit in the TRIS register puts the contents of the output instruction. For the byte oriented instruction shown in Figure
latch on the selected pin. 4-2, bits 6 down to 0 is the register address for read/write.
Controller Architecture:
As shown in Figure 3-1, the controller module is
connected via a number of inputs and outputs to the
‘datapath’ module. The controller is responsible for decoding
the current instruction in the IR (instruction register) and set
up the datapath control signals so that the data is correctly
routed from the source to the destination register accordingly
to the semantics of the instruction. As the instruction in the
IR changes so does the functionality of the Controller. The
Controller is essentially a simple state machine that asserts a
pre-determined number of signals for the various instructions.
Figure 3-8 below shows the inputs and outputs of the Figure 4-2. Instruction decoder waveforms
‘controller’ module.

Figure 4-3. ALU waveforms
As shown in Figure 4-3, alu_mux_bus and w_reg_bus
are the inputs to the ALU. The output comes out of alu_bus.
The operation to be performed is decided by the instruction
coming on ir_reg_bus. The status flags are shown on load_c,
load_dc and load_z signals.

Figure 3-8. Controller

IV. SIMULATION RESULTS
Figure 4-1 shows the top level simulation waveforms. This
Figure 4-4. Program counter waveforms
figure shows RAM, ALU and instruction decoder waveforms
also for comparison. These waveforms are explained As shown in Figure 4-4, the output of program counter
separately in subsequent figures. comes on addr_to_rom. This is changed based on the type
of instruction executed. By default, it is incremented by ‘1’.
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In case of branch instructions (indicated by branch_ins signal), CONCLUSION
the PC is incremented by value denoted on data_in. Similarly,
the current address is saved to stack through stack_out (push We are Implemented RISC based CPU Architecture. This
instruction). CPU uses hardware Architecture and two level Pipelined
Structures. This Architecture have only 35 reduced
instruction in it’s instruction set and most of the instructions
only need one machine cycle to be executed. The performance
of the CPU has been improved by replacing micro program
with direct Logic Block.This CPU gives good performance
Figure 4-5. ROM waveforms
ratherthan SISC based Architectures.the Simulation Results
shows the CPU has a good performance.
Figure 4-5 shows ROM waveforms where the address, chip
select and corresponding instruction can be seen on data.
REFERENCES
V. FPGA IMPLEMENTATION
[1] PIC16C63A/65B/73B/74B DataSheet, Microchip Technology
The design is implemented in Spartan 3E FPGA XC3S500E Inc,2000.
on Spartan 3E starter kit. The design occupies 3% of the [2] Piguet C. Low power design of 8-b embedded cool-RISC
FPGA and correspondingly maximum frequency of operation microcontroller cores. IEEE Journal of Solid-State Circuits, 1997,
is 233.91MHz. The placed design is shown in Figure 5-1. 32(7): 1067~1077
Routed design is shown in Figure 5-2. [3] OTP 8-Bit CMOS MCU with EEPROM Data Memory, USA:
Microchip Technology Inc, 1998
[4] PIC micro TM Mid-Range MCU Family Reference Manual.
Microchip Technology Inc.1997. 1~688.
[5] Mano, M. M., Computer System Archetecture, Prentice Hall,
Tsinghua University press,1997.
[6] Ma G K, Taylor F J. Multiplier policies for digital signal
processing. IEEE ASSP Magazine, 1990, 7(1): 6~20
[7] Hewlett-Packard Company (September 1987). Hewlett-Packard
Journal 38
[8] Wayne Wolf, Modern VLSI Design, USA: Printice Hall,
2001:298~299.
About Authors
S Nagakishore Bhavanam is an M.Tech Post-
Graduate of VLSI-SD from Aurora’s Techno-
Figure 5-1. Placed design Figure 5-2. Routed design
logical & Research Institute (ATRI), Depart-
The design is implemented in Spartan 3E FPGA and the ment of ECE, JNTUH. He obtained his B.Tech
results are verified using chipscope on-chip debugging tool. from S.V.V.S.N Engineering college, Ongole. He
The results obtained are shown in Figure 5-3. has 18 Months of teaching experience. He has 4
Research Papers, Published in IEEE Xplore, He
has 3 International journal Publications and has 6 Papers, Published
in International & National Conferences. His interesting Fields are
Low Power VLSI, Digital System Design, Sensor Networks, and
Communications.
Vasujadevi M idasala is an M.Tech Post-
Graduate of VLSI from Bandari Institute of
Figure 5-3. Chipscope results science and Technology, Department of ECE,
JNTUH. She obtained her B.Tech from S.V.V.S.N
For on-chip debugging, some important signals like ROM
Engineering college Ongole. She Has 4 Research
address, instruction, register address, register data input and Papers Published in International/ National
data output are probed. Based on the instruction being Journals. Her interesting Fields are Low Power
executed, we can see the signal values. The results are verified VLSI, Design for Testability.
using chipscope analyzer tool from Xilinx. Haritha M is an M.Tech Post- Graduate of VLSI
from, Aurora’s Technological & Research Institute
ACKNOWLEDGEMENT (ATRI), Department of ECE, JNTUH. She
obtained her B.Tech from T.K.R Engineering
We would like to thank the Faculty of GNI, KMIT & college Hyderabad. Her interesting Fields are
HMIT for their support. We acknowledge Mr satish Babu Microcontrollers & Signals and Signals.
help in the development and testing of our implementation
“A PIC compatible RISC CPU core Implementation for FPGA
based Configurable SOC platform for Embedded
Applications” .
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© 2011 ACEEE
DOI: 01.IJEPE.02.02. 44

A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC platform for Embedded Applications

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A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC platform for Embedded Applications