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ANALYSIS & DESIGN OF COMBINATIONAL LOGIC

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Supanna Shirguppe

The document provides instructions for a unit assignment involving simplification of logic expressions using the Variable Elimination Method (VEM) technique. It lists 3 steps - 1) simplify an expression using VEM, 2) obtain the minimal product, 3) simplify another expression using VEM. It then provides 4 logic expressions that need simplification.

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ASSIGNMENT Unit 2: 1) Simplify using VEM technique. 2) Obtain the Minimal product using VEM technique. 3) Simplify using VEM technique. bacbdYAns dcmdcbaY    : )13,12,11,7,2()15,10,9,8,5,4,3,1(),,,( ))()(())()((: )13,6,3,2()11,10,7,5,1(),,,( cabadcorcabadaAns dcmdcbaf    bddabcbaAns dcmdcbaf    : )9,8,7,2()15,14,13,6,5,4,0(),,,(
2 x1 x2 x3 x4 00 01 11 10 1 1 1 1 1 1 1 1 00 01 11 10 (a) Function 1 f 1 F1 = X1'.X3 + X1.X3' + X2.X3'.X4 x1 x2 x3 x4 00 01 11 10 1 1 1 1 1 1 1 1 1 00 01 11 10 (b) Function f 2 F2 = X1'.X3 + X1.X3' + X2.X3.X4 Multiple-output Logic Circuit Example: Given two functions, F1 and F2, of the same input variables x1.. x4, design the minimum-cost implementation.
3 f 1 f 2 x2 x3 x4 x1 x3 x1 x3 x2 x3 x4 (c) Combined circuit for f 1 f 2and Multiple-output Logic Circuit
Logic Design PART A Unit 3: ANALYSIS & DESIGN OF COMBINATIONAL LOGIC-I: General approach, Decoders-BCD decoders, Encoders.
1) Design a combinational circuit to find the 9’s complement of BCD numbers. ( 9’s complement of x = 9-x) Soln.: If the 9’s complement is represented by Y3 Y2 Y1 Y0 then, Y0=∑m(0,2,4,6,8) + ∑dc(10,11,12,13,14,15) Y1=∑m(2,3,6,7) + ∑dc(10,11,12,13,14,15) Y2=∑m(2,3,4,5) + ∑dc(10,11,12,13,14,15) Y3=∑m(0,1) + ∑dc(10,11,12,13,14,15) After simplification using K maps, we get, ,CY,BYC,Y,DY 3210 BAC  Finally draw the Logic circuit.
2) Design a combinational circuit to drive a Common Cathode seven segment display with BCD I/Ps. a b c g e d f For Common Cathode display, connect the open ends of the LED display (a, b, c…g) to Vcc to make the corresponding LEDs to glow. For Common Anode display, connect the open ends of the LED display (a, b, c…g) to Ground to make the corresponding LEDs to glow.
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
a b c g e d f For the remaining I/P combinations (1010 to 1111), O/Ps can be taken as Don’t cares (X).
Next draw K-maps for each of the O/Ps. (7 K- maps). Group the cells and obtain the simplified form of expressions for a, b, c, d, e & f. Draw the logic diagram.B 1 1 1 1 1 1 C’A’ D x x x x 1 1 x x CA a = D + CA + B + C’A’ b = . . . c = . . . d = . . .
Decoders are a class of combinational logic circuits that convert a set of I/P variables representing a code into a set of O/P variables representing a different code. They have n inputs and produce 2n outputs.
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
Practical Decoder ICs Dual 2:4 Decoder IC (74139) It has 2 active-low enable I/Ps.
3:8 Decoder IC (74138) It has 1 active-high enable I/P (G1) and 2 active-low enable I/Ps (G2A and G2B).
Implementing a 3-to-8 Decoder using a dual 2-to-4 decoder IC. Inputs: a, b, c a b c 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 Y0 Y7Y1 Y2 Y3 Y4 Y5 Y6 1G 1A (LSB) 1B(MSB) 2A 2B 2Y02G 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 74139 a b c Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Inputs: D, C, B, A Outputs: Y0 – Y15 When D = 0, top decoder is enabled, when D = 1,bottom decoder is enabled. En’ is enable I/P. Implementing a 4-to-16 Decoder using two 3-to-8 decoder ICs.
Implementinga5-to-32Decoderusingfour 3-to-8decoders&a2:4decoder. Inputs: E, D, C, B, A Outputs: Y0 – Y31 Enable I/Ps: EN1, EN2A , EN2B EN2A EN2B EN1
Decoders with Active high, active low O/Ps • Active-High / Active-Low I1 I0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 I1 I0 Y3 Y2 Y1 Y0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 Binary Decoder I1 I0 Y3 Y2 Y1 Y0 I1 I0 Y3 Y2 Y1 Y0 Binary Decoder I1 I0 Y3 Y2 Y1 Y0
SOP function implementation with a decoder having Active-High O/Ps. f(a,b,c)=∑m(1,2,3,7)= m1+ m2+ m3+ m7 f(a,b,c) A B C Y4 En Y5 Y6 Y7 Y0 Y1 Y2 Y3 a b c (MSB) (LSB) m1 m2 m3 m7 OR
SOP function implementation with a decoder having Active-Low O/Ps. f(a,b,c)=∑m(1,2,3,7) = m1+ m2+ m3+ m7 A B C Y4 En Y5 Y6 Y7 Y0 Y1 Y2 Y3 a f(a,b,c) NAND b c (MSB) (LSB) OR m1 m2 m3 m7
POS function implementation with a decoder having Active-High O/Ps. f(a,b,c) = ∏M (1,2,3,7)=M1 . M2 . M3 . M7 = 7321 m.m.m.m A B C Y4 En Y5 Y6 Y7 Y0 Y1 Y2 Y3 a f(a,b,c) NOR b c (MSB) (LSB) AND m1 m2 m3 m7
POS function implementation with a decoder having Active-Low O/Ps. f(a,b,c) = ∏M (1,2,3,7)=M1.M2.M3.M7 = 7321 m.m.m.m A B C En a f(a,b,c) b c (MSB) (LSB) Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3
Implementation Using Decoders • Each output is a minterm • All minterms are produced • Sum the required minterms Example: Full Adder S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7) I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C
Full Adder Implementation Using Decoders 26 / 65 I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C
Decoders can be used as Minterm or Maxterm generators. Hence they can be used to realize a function using an external gate. 1) Realize f(a,b) = ∑m(0,2) using 74139 IC. 1G 1A (LSB) 1B(MSB) 2A 2B 2Y02G 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 74139 a f(a,b)b
2) Realize f(a,b,c) = ∑m(1,3,6,7) using a decoder IC. A (LSB) B G2A G2B Y4G1 Y5 Y6 Y7 Y0 Y1 Y2 Y3 74138 C(MSB) Vcc f b a c 1G 1A (LSB) 1B(MSB) 2A 2B 2Y02G 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 74139 b a c f or
1) Realize the following functions expressed in Maxterm form in two possible ways using 3: 8 decoder. 2) Implement the following multiple output function using 74LS138 IC and gates. 3) Implement the following function pairs using two 3:8 decoder ICs. 4) Design a logic circuit using a 3:8 logic decoder that has active low data inputs, an active high enable and active low data outputs. Use such a decoder to realize the full adder circuit. 5) Implement the following function pairs using 74138 and gates with minimum number of inputs.  )7,6,3,1(),,( 0122 Mxxxf )7,6,2,1(),,( 0121 Mxxxf   )7,6,3,2(),,()7,5,4,1(),,( 21 Mcbafmcbaf )13,9,7,3(),,,()15,14,10,8,4,0(),,,( 21   mdcbafmdcbaf )7,5,4,2,1(),,()4,2,0(),,( 21   mcbafmcbaf
6) Implement the following function pairs using 74138 and gates with minimum number of inputs. 7) Implement a Full Subtractor using a) 74138 IC b) 74139 IC. 8) Implement a Full Adder using a) 74138 IC b) 74139 IC. )6,5,3,2,1(),,()7,6,5,1,0(),,( 21   mcbafmcbaf
1) 7442 (8421 BCD to decimal decoder) 1 2 4 8 1 2 3 4 0 6 7 8 9 5 Decimal BCD
2) 7447 IC (BCD to 7 segment display decoder driver) A B C D b c d e a g fLT RBI BI/RBO
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
BCD to 7 segment display decoder driver
They have 2n inputs and produce n outputs.
A priority encoder includes the necessary logic to ensure that when two or more inputs are activated, the output code will correspond to the highest-numbered input. PRIORITY ENCODER
Design a 4 bit priority encoder and implement using gates. VALID O/P
Group select (GS) goes low when any of the I/Ps to the encoder is active & the encoder is enabled. It is used to indicate that priority encoded data is present at the O/P. Enable out (EO) is used as enable I/P to the next lower priority encoder. It goes low ( & enables the next lower priority encoder) when there is no priority event connected to the IC.
Logic Design PART A Unit 4: ANALYSIS & DESIGN OF COMBINATIONAL LOGIC-II: Digital multiplexers:Using MUXs as Boolean function generators. Adders & Subtractors: cascading full adders, Look ahead carry adder, Binary comparators. Design methods of building blocks of combinational logics.
• It allows digital information from several sources to be routed onto a single O/P line. • 2n data inputs • ‘n’ selection inputs • a single output • Selection inputs determine the input that should be connected to the output. S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 MUXY I0 I1 I2 I3 S1 S0
Data inputs selection inputs Strobe: Enable I/P 4:1 MUX implementation I1 I0 S1 Y I2 I3 S0
301201101001 ISSISSISSISSO  4:1 MUX implementation (without strobe I/P)
1) 74153 IC (Dual 4:1 MUX) Select I/Ps 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y Enabl e Select I/Ps Data I/Ps O/P EN B A D0 D1 D2 D3 Y 1 X X X X X X 0 0 0 0 0 X X X 0 0 0 0 1 X X X 1 0 0 1 X 0 X X 0 0 0 1 X 1 X X 1 0 1 0 X X 0 X 0 0 1 0 X X 1 X 1 0 1 1 X X X 0 0 0 1 1 X X X 1 1 T T for one of the decoders
2) 74151 IC (8:1 MUX) Enable Select I/Ps O/P s EN S2 S1 S0 O O 1 X X X 0 1 0 0 0 0 I0 I0 0 0 0 1 I1 I1 0 0 1 0 I2 I2 0 0 1 1 I3 I3 0 1 0 0 I4 I4 0 1 0 1 I5 I5 0 1 1 0 I6 I6 0 1 1 1 I7 I7
EXPANDING MULTIPLEXERS 1) Design a 32:1 MUX using four 8:1 MUXs & a 2:4 decoder. S0 D0D0 D31 EN B A(LSB) Y C S1 S2 D7 D0 EN B A(LSB) Y C D7 D0 EN B A(LSB) Y C D7 D0 EN B A(LSB) Y C D7 D7 D8 D15 D16 D23 D24 S3 S4 2:4 decoder
EXPANDING MULTIPLEXERS 2) Design a 32:1 MUX using two 74150 ICs. EN A(LSB) Y C D15 D0 D B EN A(LSB) Y C D15 D0 D B D0 D15 D16 D31 S1 S0 S2 S3 S4
EXPANDING MULTIPLEXERS 3) Design a 4 bit MUX system using two 74153 ICs. 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y EN SA0 SB0 SC0 SD0 SA1 SB1 SC1 SD1 SA2 SB2 SC2 SD2 SA3 SB3 SC3 SD3 4 bit data O/P S0 S1
Multiplexers as Boolean Function generators 1) Implement using an 8:1 MUX. f(a,b,c)=∑m(1,2,3,7) D0 D1 D2 D3 D4 D5 D6 D7 8:1 S 0 S 1 S2 a b c EN Vcc f(a,b,c)
2) Implement using a 4:1 MUX. f(a,b,c)=∑m(1,3,5,6) Decimal a b c f I/P 0 0 0 0 0 C 1 0 0 1 1 2 0 1 0 0 C 3 0 1 1 1 4 1 0 0 0 C 5 1 0 1 1 6 1 1 0 1 C 7 1 1 1 0 (MEV) We shall use a & b as select inputs. C 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y f a b S0S1
3) Implement using a 4:1 MUX with b, c as select inputs. f(a,b,c)=∑m(0,1,2,3,7) Decimal b c a f I/P 0 0 0 0 1 a4 0 0 1 0 1 0 1 0 1 a5 0 1 1 0 2 1 0 0 1 a6 1 0 1 0 3 1 1 0 1 1 7 1 1 1 1 a 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y f b c Vcc Select I/Ps (MEV) S0S1
4) Implement using a 4:1 MUX with a, b as select inputs. f(a,b,c,d)=∑m(0,1,5,6,7,9,10,15) c 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y f a b d a b c d f I/P 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 c dc dc cd Select I/Ps S0S1
OR Use two 4:1 MUXes & OR gate to build an 8:1 MUX & implement the function. f a b c d f I/P 0 0 0 0 1 D0=1 0 0 0 1 1 0 0 1 0 0 D1=0 0 0 1 1 0 0 1 0 0 0 D2=d 0 1 0 1 1 0 1 1 0 1 D3=1 0 1 1 1 1 1 0 0 0 0 D4=d 1 0 0 1 1 1 0 1 0 1 D5=d 1 0 1 1 0 1 1 0 0 0 D6=0 1 1 0 1 0 1 1 1 0 0 D7=d 1 1 1 1 1 S2 S1 S0 f(a,b,c,d)=∑m(0,1,5,6,7,9,10,15) a 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 2Y b c 1 0 d 1 d d d 0 1Y
Implementation of 3 I/P Majority function using 4:1 MUX
DeMultiplexers DeMUXI Y3 Y2 Y1 Y0S1 S0 S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 I 0 1 0 0 I 0 1 0 0 I 0 0 1 1 I 0 0 0 I Y3 Y2 Y1 Y0 S0 S1
DeMultiplexers / Decoders Binary Decoder I1 I0 E Y3 Y2 Y1 Y0 E I1 I0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 DeMUXI Y3 Y2 Y1 Y0S1 S0 S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 I 0 1 0 0 I 0 1 0 0 I 0 0 1 1 I 0 0 0
Assignment 1) Implement f(a,b,c)=∑m(0,1,2,7) using 74153 IC with a,c as select I/Ps. Ans: D0=1, D1=b’, D2=0, D3=b. 2) Implement f(a,b,c,d)= ∑m(0,1,5,6,7,9,10,14,15) using an 8:1 MUX IC. Ans: D0=1, D1=0, D2=d, D3=1, D4=d, D5=d’, D6=0, D7=1.
Adders  Half-adder ◦ Adds two bits  Produces a sum and carry ◦ Problem: Cannot use it to build larger inputs  Full-adder ◦ Adds three 1-bit values  Like half-adder, it produces a sum and carry ◦ Allows building N-bit adders  Simple technique  Connect Cout of one adder to Cin of the next  These are called ripple-carry adders
BA BABA(1,2)    AB Half adder & Full adder using basic gates CinBA ABCCBACBACBAS inininin   ABB)CinA( ABCCABCBABCAC ininininout    (1,2,4,7)  (3,5,6,7)
CinBA ABCCBACBACBAS inininin   ABB)CinA( ABCCABCBABCAC ininininout   Full adder using 2 half adders & OR gate
Half adder & Full adder using NAND gates A B C
BinBA ABBBBABBABBAD inininin   Half subtractor & Full subtractor using basic gates BA)BinBA( ABBBBABBABBAB ininininout   BA BABA(1,2)    BA A B D Bout 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 A B Bin D Bout 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1  (1,2,4,7)  (1,2,3,7)
Half subtractor & Full subtractor using only NAND gates
4 bit Ripple-carry Adder Carry-out of one stage is given as Carry-in to the next stage Full adder.
• Ripple-carry adders can be slow – Delay is proportional to number of bits • Carry look-ahead adders – Eliminate the delay of ripple-carry adders, hence fast. – Carry-ins are generated independently. They do not depend on Cout of previous stage. – Requires complex circuits
4 bit parallel Subtractor 4 bit Parallel Adder/ Subtractor
CARRY LOOK-AHEAD ADDER – Eliminate the delay of ripple-carry adders – Carry-ins are generated independently Here we define 2 functions: Carry Propagate & Carry Generate iii BAP  iii BAG  i1iii 1-iiiiii GCPCCarry &CPCBASSumThen,    4342341234012344344 32312301233233 2120122122 101111 GGPGPPGPPPCPPPPGCPC GGPGPPCPPPGCPC GGPCPPGCPC GCPGCPCow,     inN Hence Carry-outs are independent of Carry-ins from previous stages.
C0 C0 C1 C2 C3 C4 S5=C4 344 CPS  233 CPS  122 CPS  011 CPS 
Cascading two 7483 ICs to form an 8 bit parallel adder Sum bits (O/P) Cout(C4) Cin(C0)
DECIMAL ADDERS Digital systems handle decimal numbers in the form of BCD numbers. • Decimal numbers from 0-9 are represented in BCD form from 0000-1001. • Each decimal digit is represented by a 4 bit binary number. • A BCD digit can’t be >9. A BCD adder is one that adds 2 BCD digits & produces a Sum digit also in BCD.
Consider the following 3 cases. a) Sum bits is <=9 & Carry=0 Eg. BCD addition : 3 + 5 = 8 (1000 <= 9) 0011 + 0101 ------ 1000  Valid BCD number  Correct answer Hence no correction is required. b) Sum bits >9 (Carry will be 0 in this case) Eg. BCD addition : 8 + 4 = 12 (1100 > 9) 1000 + 0100 1100  Invalid BCD  + 0110 0001 0010  12 in BCD Correct answer Hence Correction is required. Add 0110 (six) to get correct answer. 21
c) Sum bits <= 9 & Carry=1 Eg. BCD addition : 8 + 9 = 17 (0001 <= 9) 1000 + 1001 0001 0001  11 in BCD But incorrect answer. + 0110 Add 0110 (six) 0001 0111  17 in BCD Correct answer  71 Hence, 1) If 4 bit sum is <=9, no correction is required. 2) If 4 bit sum is > 9 OR if carry is generated from the 4 bit addition, the sum is incorrect and therefore 0110 is to be added to the 4 bit sum. Therefore to implement a BCD adder, we require 1) 4 bit binary adder for initial addition. 2) Logic circuit to detect if sum is > 9 OR carry =1 3) One more 4 bit adder to add 0110 to the sum if it is > 9 or carry=1.
Logic circuit to detect if Sum > 9 Decimal S3 S2 S1 S0 Y 0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 1 11 1 0 1 1 1 12 1 0 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 S1 S0 S3 S2 Y = S3S1 + S3S2 Y S1 S2 S3 0110 IS TO BE ADDED IF SUM > 9 OR CARRY=1 0110 to be added to sum S1 S2 S3 Carry from initial addition
BCD ADDER CIRCUIT 4 bit Binary Adder 4 bit Binary Adder 0 1 1 0 B3B2B1B0 A3A2A1A0 Cin Cout Cin (ignored) S3 S2 S1 S0Carry out(S4) Cout
ANALYSIS & DESIGN OF COMBINATIONAL LOGIC
1) 1-bit Comparator x y x>y x=y x<y 1 bit CMP COMPARATORS x y x>y x=y x<y 0 0 0 1 1 0 1 1 1 00 0 10 0 01 1 00
BA 22 2 bit comparator A<BA=BA>B A1 A0 B1 B0 A>B A=B A<B 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 110011 11010010 0011 110011 00111010 BABA)BA( BABBABAAB)(A )BA)(BA(B)(A BAB)ABA( BAABABBAB)(A      2) 2-bit Comparator
A1 A0 B1 B0 E G L 2 bit comparator 7411 7411
3) 4-bit magnitude comparator chip (7485)
8 bit Comparator by cascading two 7485 ICs If I(A<B) I(A=B) I(A>B) A<B A=B A>B A7A6A5A4 = B7B6B5B4 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 A7A6A5A4 < B7B6B5B4 X X X 1 0 0 A7A6A5A4 > B7B6B5B4 X X X 0 0 1 NOTE THIS

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ANALYSIS & DESIGN OF COMBINATIONAL LOGIC

  • 1. ASSIGNMENT Unit 2: 1) Simplify using VEM technique. 2) Obtain the Minimal product using VEM technique. 3) Simplify using VEM technique. bacbdYAns dcmdcbaY    : )13,12,11,7,2()15,10,9,8,5,4,3,1(),,,( ))()(())()((: )13,6,3,2()11,10,7,5,1(),,,( cabadcorcabadaAns dcmdcbaf    bddabcbaAns dcmdcbaf    : )9,8,7,2()15,14,13,6,5,4,0(),,,(
  • 2. 2 x1 x2 x3 x4 00 01 11 10 1 1 1 1 1 1 1 1 00 01 11 10 (a) Function 1 f 1 F1 = X1'.X3 + X1.X3' + X2.X3'.X4 x1 x2 x3 x4 00 01 11 10 1 1 1 1 1 1 1 1 1 00 01 11 10 (b) Function f 2 F2 = X1'.X3 + X1.X3' + X2.X3.X4 Multiple-output Logic Circuit Example: Given two functions, F1 and F2, of the same input variables x1.. x4, design the minimum-cost implementation.
  • 3. 3 f 1 f 2 x2 x3 x4 x1 x3 x1 x3 x2 x3 x4 (c) Combined circuit for f 1 f 2and Multiple-output Logic Circuit
  • 4. Logic Design PART A Unit 3: ANALYSIS & DESIGN OF COMBINATIONAL LOGIC-I: General approach, Decoders-BCD decoders, Encoders.
  • 5. 1) Design a combinational circuit to find the 9’s complement of BCD numbers. ( 9’s complement of x = 9-x) Soln.: If the 9’s complement is represented by Y3 Y2 Y1 Y0 then, Y0=∑m(0,2,4,6,8) + ∑dc(10,11,12,13,14,15) Y1=∑m(2,3,6,7) + ∑dc(10,11,12,13,14,15) Y2=∑m(2,3,4,5) + ∑dc(10,11,12,13,14,15) Y3=∑m(0,1) + ∑dc(10,11,12,13,14,15) After simplification using K maps, we get, ,CY,BYC,Y,DY 3210 BAC  Finally draw the Logic circuit.
  • 6. 2) Design a combinational circuit to drive a Common Cathode seven segment display with BCD I/Ps. a b c g e d f For Common Cathode display, connect the open ends of the LED display (a, b, c…g) to Vcc to make the corresponding LEDs to glow. For Common Anode display, connect the open ends of the LED display (a, b, c…g) to Ground to make the corresponding LEDs to glow.
  • 8. a b c g e d f For the remaining I/P combinations (1010 to 1111), O/Ps can be taken as Don’t cares (X).
  • 9. Next draw K-maps for each of the O/Ps. (7 K- maps). Group the cells and obtain the simplified form of expressions for a, b, c, d, e & f. Draw the logic diagram.B 1 1 1 1 1 1 C’A’ D x x x x 1 1 x x CA a = D + CA + B + C’A’ b = . . . c = . . . d = . . .
  • 10. Decoders are a class of combinational logic circuits that convert a set of I/P variables representing a code into a set of O/P variables representing a different code. They have n inputs and produce 2n outputs.
  • 15. Practical Decoder ICs Dual 2:4 Decoder IC (74139) It has 2 active-low enable I/Ps.
  • 16. 3:8 Decoder IC (74138) It has 1 active-high enable I/P (G1) and 2 active-low enable I/Ps (G2A and G2B).
  • 17. Implementing a 3-to-8 Decoder using a dual 2-to-4 decoder IC. Inputs: a, b, c a b c 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 Y0 Y7Y1 Y2 Y3 Y4 Y5 Y6 1G 1A (LSB) 1B(MSB) 2A 2B 2Y02G 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 74139 a b c Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
  • 18. Inputs: D, C, B, A Outputs: Y0 – Y15 When D = 0, top decoder is enabled, when D = 1,bottom decoder is enabled. En’ is enable I/P. Implementing a 4-to-16 Decoder using two 3-to-8 decoder ICs.
  • 19. Implementinga5-to-32Decoderusingfour 3-to-8decoders&a2:4decoder. Inputs: E, D, C, B, A Outputs: Y0 – Y31 Enable I/Ps: EN1, EN2A , EN2B EN2A EN2B EN1
  • 20. Decoders with Active high, active low O/Ps • Active-High / Active-Low I1 I0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 I1 I0 Y3 Y2 Y1 Y0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 Binary Decoder I1 I0 Y3 Y2 Y1 Y0 I1 I0 Y3 Y2 Y1 Y0 Binary Decoder I1 I0 Y3 Y2 Y1 Y0
  • 21. SOP function implementation with a decoder having Active-High O/Ps. f(a,b,c)=∑m(1,2,3,7)= m1+ m2+ m3+ m7 f(a,b,c) A B C Y4 En Y5 Y6 Y7 Y0 Y1 Y2 Y3 a b c (MSB) (LSB) m1 m2 m3 m7 OR
  • 22. SOP function implementation with a decoder having Active-Low O/Ps. f(a,b,c)=∑m(1,2,3,7) = m1+ m2+ m3+ m7 A B C Y4 En Y5 Y6 Y7 Y0 Y1 Y2 Y3 a f(a,b,c) NAND b c (MSB) (LSB) OR m1 m2 m3 m7
  • 23. POS function implementation with a decoder having Active-High O/Ps. f(a,b,c) = ∏M (1,2,3,7)=M1 . M2 . M3 . M7 = 7321 m.m.m.m A B C Y4 En Y5 Y6 Y7 Y0 Y1 Y2 Y3 a f(a,b,c) NOR b c (MSB) (LSB) AND m1 m2 m3 m7
  • 24. POS function implementation with a decoder having Active-Low O/Ps. f(a,b,c) = ∏M (1,2,3,7)=M1.M2.M3.M7 = 7321 m.m.m.m A B C En a f(a,b,c) b c (MSB) (LSB) Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3
  • 25. Implementation Using Decoders • Each output is a minterm • All minterms are produced • Sum the required minterms Example: Full Adder S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7) I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C
  • 26. Full Adder Implementation Using Decoders 26 / 65 I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C
  • 27. Decoders can be used as Minterm or Maxterm generators. Hence they can be used to realize a function using an external gate. 1) Realize f(a,b) = ∑m(0,2) using 74139 IC. 1G 1A (LSB) 1B(MSB) 2A 2B 2Y02G 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 74139 a f(a,b)b
  • 28. 2) Realize f(a,b,c) = ∑m(1,3,6,7) using a decoder IC. A (LSB) B G2A G2B Y4G1 Y5 Y6 Y7 Y0 Y1 Y2 Y3 74138 C(MSB) Vcc f b a c 1G 1A (LSB) 1B(MSB) 2A 2B 2Y02G 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 74139 b a c f or
  • 29. 1) Realize the following functions expressed in Maxterm form in two possible ways using 3: 8 decoder. 2) Implement the following multiple output function using 74LS138 IC and gates. 3) Implement the following function pairs using two 3:8 decoder ICs. 4) Design a logic circuit using a 3:8 logic decoder that has active low data inputs, an active high enable and active low data outputs. Use such a decoder to realize the full adder circuit. 5) Implement the following function pairs using 74138 and gates with minimum number of inputs.  )7,6,3,1(),,( 0122 Mxxxf )7,6,2,1(),,( 0121 Mxxxf   )7,6,3,2(),,()7,5,4,1(),,( 21 Mcbafmcbaf )13,9,7,3(),,,()15,14,10,8,4,0(),,,( 21   mdcbafmdcbaf )7,5,4,2,1(),,()4,2,0(),,( 21   mcbafmcbaf
  • 30. 6) Implement the following function pairs using 74138 and gates with minimum number of inputs. 7) Implement a Full Subtractor using a) 74138 IC b) 74139 IC. 8) Implement a Full Adder using a) 74138 IC b) 74139 IC. )6,5,3,2,1(),,()7,6,5,1,0(),,( 21   mcbafmcbaf
  • 31. 1) 7442 (8421 BCD to decimal decoder) 1 2 4 8 1 2 3 4 0 6 7 8 9 5 Decimal BCD
  • 32. 2) 7447 IC (BCD to 7 segment display decoder driver) A B C D b c d e a g fLT RBI BI/RBO
  • 34. BCD to 7 segment display decoder driver
  • 35. They have 2n inputs and produce n outputs.
  • 36. A priority encoder includes the necessary logic to ensure that when two or more inputs are activated, the output code will correspond to the highest-numbered input. PRIORITY ENCODER
  • 37. Design a 4 bit priority encoder and implement using gates. VALID O/P
  • 38. Group select (GS) goes low when any of the I/Ps to the encoder is active & the encoder is enabled. It is used to indicate that priority encoded data is present at the O/P. Enable out (EO) is used as enable I/P to the next lower priority encoder. It goes low ( & enables the next lower priority encoder) when there is no priority event connected to the IC.
  • 39. Logic Design PART A Unit 4: ANALYSIS & DESIGN OF COMBINATIONAL LOGIC-II: Digital multiplexers:Using MUXs as Boolean function generators. Adders & Subtractors: cascading full adders, Look ahead carry adder, Binary comparators. Design methods of building blocks of combinational logics.
  • 40. • It allows digital information from several sources to be routed onto a single O/P line. • 2n data inputs • ‘n’ selection inputs • a single output • Selection inputs determine the input that should be connected to the output. S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 MUXY I0 I1 I2 I3 S1 S0
  • 41. Data inputs selection inputs Strobe: Enable I/P 4:1 MUX implementation I1 I0 S1 Y I2 I3 S0
  • 42. 301201101001 ISSISSISSISSO  4:1 MUX implementation (without strobe I/P)
  • 43. 1) 74153 IC (Dual 4:1 MUX) Select I/Ps 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y Enabl e Select I/Ps Data I/Ps O/P EN B A D0 D1 D2 D3 Y 1 X X X X X X 0 0 0 0 0 X X X 0 0 0 0 1 X X X 1 0 0 1 X 0 X X 0 0 0 1 X 1 X X 1 0 1 0 X X 0 X 0 0 1 0 X X 1 X 1 0 1 1 X X X 0 0 0 1 1 X X X 1 1 T T for one of the decoders
  • 44. 2) 74151 IC (8:1 MUX) Enable Select I/Ps O/P s EN S2 S1 S0 O O 1 X X X 0 1 0 0 0 0 I0 I0 0 0 0 1 I1 I1 0 0 1 0 I2 I2 0 0 1 1 I3 I3 0 1 0 0 I4 I4 0 1 0 1 I5 I5 0 1 1 0 I6 I6 0 1 1 1 I7 I7
  • 45. EXPANDING MULTIPLEXERS 1) Design a 32:1 MUX using four 8:1 MUXs & a 2:4 decoder. S0 D0D0 D31 EN B A(LSB) Y C S1 S2 D7 D0 EN B A(LSB) Y C D7 D0 EN B A(LSB) Y C D7 D0 EN B A(LSB) Y C D7 D7 D8 D15 D16 D23 D24 S3 S4 2:4 decoder
  • 46. EXPANDING MULTIPLEXERS 2) Design a 32:1 MUX using two 74150 ICs. EN A(LSB) Y C D15 D0 D B EN A(LSB) Y C D15 D0 D B D0 D15 D16 D31 S1 S0 S2 S3 S4
  • 47. EXPANDING MULTIPLEXERS 3) Design a 4 bit MUX system using two 74153 ICs. 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y EN SA0 SB0 SC0 SD0 SA1 SB1 SC1 SD1 SA2 SB2 SC2 SD2 SA3 SB3 SC3 SD3 4 bit data O/P S0 S1
  • 48. Multiplexers as Boolean Function generators 1) Implement using an 8:1 MUX. f(a,b,c)=∑m(1,2,3,7) D0 D1 D2 D3 D4 D5 D6 D7 8:1 S 0 S 1 S2 a b c EN Vcc f(a,b,c)
  • 49. 2) Implement using a 4:1 MUX. f(a,b,c)=∑m(1,3,5,6) Decimal a b c f I/P 0 0 0 0 0 C 1 0 0 1 1 2 0 1 0 0 C 3 0 1 1 1 4 1 0 0 0 C 5 1 0 1 1 6 1 1 0 1 C 7 1 1 1 0 (MEV) We shall use a & b as select inputs. C 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y f a b S0S1
  • 50. 3) Implement using a 4:1 MUX with b, c as select inputs. f(a,b,c)=∑m(0,1,2,3,7) Decimal b c a f I/P 0 0 0 0 1 a4 0 0 1 0 1 0 1 0 1 a5 0 1 1 0 2 1 0 0 1 a6 1 0 1 0 3 1 1 0 1 1 7 1 1 1 1 a 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y f b c Vcc Select I/Ps (MEV) S0S1
  • 51. 4) Implement using a 4:1 MUX with a, b as select inputs. f(a,b,c,d)=∑m(0,1,5,6,7,9,10,15) c 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 1Y 2Y f a b d a b c d f I/P 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 c dc dc cd Select I/Ps S0S1
  • 52. OR Use two 4:1 MUXes & OR gate to build an 8:1 MUX & implement the function. f a b c d f I/P 0 0 0 0 1 D0=1 0 0 0 1 1 0 0 1 0 0 D1=0 0 0 1 1 0 0 1 0 0 0 D2=d 0 1 0 1 1 0 1 1 0 1 D3=1 0 1 1 1 1 1 0 0 0 0 D4=d 1 0 0 1 1 1 0 1 0 1 D5=d 1 0 1 1 0 1 1 0 0 0 D6=0 1 1 0 1 0 1 1 1 0 0 D7=d 1 1 1 1 1 S2 S1 S0 f(a,b,c,d)=∑m(0,1,5,6,7,9,10,15) a 1D0 1D1 1D2 1D3 1EN B A(LSB) 2D0 2D1 2D2 2D3 2EN 2Y b c 1 0 d 1 d d d 0 1Y
  • 53. Implementation of 3 I/P Majority function using 4:1 MUX
  • 54. DeMultiplexers DeMUXI Y3 Y2 Y1 Y0S1 S0 S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 I 0 1 0 0 I 0 1 0 0 I 0 0 1 1 I 0 0 0 I Y3 Y2 Y1 Y0 S0 S1
  • 55. DeMultiplexers / Decoders Binary Decoder I1 I0 E Y3 Y2 Y1 Y0 E I1 I0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 DeMUXI Y3 Y2 Y1 Y0S1 S0 S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 I 0 1 0 0 I 0 1 0 0 I 0 0 1 1 I 0 0 0
  • 56. Assignment 1) Implement f(a,b,c)=∑m(0,1,2,7) using 74153 IC with a,c as select I/Ps. Ans: D0=1, D1=b’, D2=0, D3=b. 2) Implement f(a,b,c,d)= ∑m(0,1,5,6,7,9,10,14,15) using an 8:1 MUX IC. Ans: D0=1, D1=0, D2=d, D3=1, D4=d, D5=d’, D6=0, D7=1.
  • 57. Adders  Half-adder ◦ Adds two bits  Produces a sum and carry ◦ Problem: Cannot use it to build larger inputs  Full-adder ◦ Adds three 1-bit values  Like half-adder, it produces a sum and carry ◦ Allows building N-bit adders  Simple technique  Connect Cout of one adder to Cin of the next  These are called ripple-carry adders
  • 58. BA BABA(1,2)    AB Half adder & Full adder using basic gates CinBA ABCCBACBACBAS inininin   ABB)CinA( ABCCABCBABCAC ininininout    (1,2,4,7)  (3,5,6,7)
  • 60. Half adder & Full adder using NAND gates A B C
  • 61. BinBA ABBBBABBABBAD inininin   Half subtractor & Full subtractor using basic gates BA)BinBA( ABBBBABBABBAB ininininout   BA BABA(1,2)    BA A B D Bout 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 A B Bin D Bout 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1  (1,2,4,7)  (1,2,3,7)
  • 62. Half subtractor & Full subtractor using only NAND gates
  • 63. 4 bit Ripple-carry Adder Carry-out of one stage is given as Carry-in to the next stage Full adder.
  • 64. • Ripple-carry adders can be slow – Delay is proportional to number of bits • Carry look-ahead adders – Eliminate the delay of ripple-carry adders, hence fast. – Carry-ins are generated independently. They do not depend on Cout of previous stage. – Requires complex circuits
  • 65. 4 bit parallel Subtractor 4 bit Parallel Adder/ Subtractor
  • 66. CARRY LOOK-AHEAD ADDER – Eliminate the delay of ripple-carry adders – Carry-ins are generated independently Here we define 2 functions: Carry Propagate & Carry Generate iii BAP  iii BAG  i1iii 1-iiiiii GCPCCarry &CPCBASSumThen,    4342341234012344344 32312301233233 2120122122 101111 GGPGPPGPPPCPPPPGCPC GGPGPPCPPPGCPC GGPCPPGCPC GCPGCPCow,     inN Hence Carry-outs are independent of Carry-ins from previous stages.
  • 67. C0 C0 C1 C2 C3 C4 S5=C4 344 CPS  233 CPS  122 CPS  011 CPS 
  • 68. Cascading two 7483 ICs to form an 8 bit parallel adder Sum bits (O/P) Cout(C4) Cin(C0)
  • 69. DECIMAL ADDERS Digital systems handle decimal numbers in the form of BCD numbers. • Decimal numbers from 0-9 are represented in BCD form from 0000-1001. • Each decimal digit is represented by a 4 bit binary number. • A BCD digit can’t be >9. A BCD adder is one that adds 2 BCD digits & produces a Sum digit also in BCD.
  • 70. Consider the following 3 cases. a) Sum bits is <=9 & Carry=0 Eg. BCD addition : 3 + 5 = 8 (1000 <= 9) 0011 + 0101 ------ 1000  Valid BCD number  Correct answer Hence no correction is required. b) Sum bits >9 (Carry will be 0 in this case) Eg. BCD addition : 8 + 4 = 12 (1100 > 9) 1000 + 0100 1100  Invalid BCD  + 0110 0001 0010  12 in BCD Correct answer Hence Correction is required. Add 0110 (six) to get correct answer. 21
  • 71. c) Sum bits <= 9 & Carry=1 Eg. BCD addition : 8 + 9 = 17 (0001 <= 9) 1000 + 1001 0001 0001  11 in BCD But incorrect answer. + 0110 Add 0110 (six) 0001 0111  17 in BCD Correct answer  71 Hence, 1) If 4 bit sum is <=9, no correction is required. 2) If 4 bit sum is > 9 OR if carry is generated from the 4 bit addition, the sum is incorrect and therefore 0110 is to be added to the 4 bit sum. Therefore to implement a BCD adder, we require 1) 4 bit binary adder for initial addition. 2) Logic circuit to detect if sum is > 9 OR carry =1 3) One more 4 bit adder to add 0110 to the sum if it is > 9 or carry=1.
  • 72. Logic circuit to detect if Sum > 9 Decimal S3 S2 S1 S0 Y 0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 1 11 1 0 1 1 1 12 1 0 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 S1 S0 S3 S2 Y = S3S1 + S3S2 Y S1 S2 S3 0110 IS TO BE ADDED IF SUM > 9 OR CARRY=1 0110 to be added to sum S1 S2 S3 Carry from initial addition
  • 73. BCD ADDER CIRCUIT 4 bit Binary Adder 4 bit Binary Adder 0 1 1 0 B3B2B1B0 A3A2A1A0 Cin Cout Cin (ignored) S3 S2 S1 S0Carry out(S4) Cout
  • 75. 1) 1-bit Comparator x y x>y x=y x<y 1 bit CMP COMPARATORS x y x>y x=y x<y 0 0 0 1 1 0 1 1 1 00 0 10 0 01 1 00
  • 76. BA 22 2 bit comparator A<BA=BA>B A1 A0 B1 B0 A>B A=B A<B 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 110011 11010010 0011 110011 00111010 BABA)BA( BABBABAAB)(A )BA)(BA(B)(A BAB)ABA( BAABABBAB)(A      2) 2-bit Comparator
  • 77. A1 A0 B1 B0 E G L 2 bit comparator 7411 7411
  • 78. 3) 4-bit magnitude comparator chip (7485)
  • 79. 8 bit Comparator by cascading two 7485 ICs If I(A<B) I(A=B) I(A>B) A<B A=B A>B A7A6A5A4 = B7B6B5B4 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 A7A6A5A4 < B7B6B5B4 X X X 1 0 0 A7A6A5A4 > B7B6B5B4 X X X 0 0 1 NOTE THIS