Arm cm3 architecture_and_programmer_model
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The document provides an overview of the ARM Cortex-M3 architecture and programmer's model. It discusses the Cortex-M3 register set including general purpose registers, stack pointers, link register, program counter, and special registers. It also covers the Cortex-M3 operation modes of handler mode and thread mode, as well as privileged and user access levels. Finally, it describes exceptions and interrupts handling in Cortex-M3 through vector tables.
![Special Registers (cont..)
● The Control Register
● Used to define privilege level and SP selection
● Has only 2 bits
– CONTROL[1]
– CONTROL[0]](https://image.slidesharecdn.com/armcm3architectureandprogrammermodel-150206235732-conversion-gate02/85/Arm-cm3-architecture_and_programmer_model-26-320.jpg)
![Special Registers (cont..)
– CONTROL[1]
● Gives the stack status
● It is always 0 in handler mode
● Either 0 or 1 in thread/base level
● Writable when the core is in thread mode and privileged level
● Writing to this bit is not allowed in user state and handler mode](https://image.slidesharecdn.com/armcm3architectureandprogrammermodel-150206235732-conversion-gate02/85/Arm-cm3-architecture_and_programmer_model-27-320.jpg)
![Special Registers (cont..)
– CONTROL[0]
● Gives the mode status
● This bit is writable only in privileged state
● To change this bit when in user state, triger an interrupt and
change this in exception handler](https://image.slidesharecdn.com/armcm3architectureandprogrammermodel-150206235732-conversion-gate02/85/Arm-cm3-architecture_and_programmer_model-28-320.jpg)
Arm cm3 architecture_and_programmer_model
- 1. ARM Cortex-M3 Architecture and Programmer's Model Akshay Raut C-DAC Hyderabadby Ganesh Naik
- 2. AGENDA ● What is an Embedded System ● Characteristics of an Embedded System ● Components of an Embedded System ● ARM Cortex-M3 Fundamentals/Overview – Registers – Operation Modes – Exceptions and Interrupts – Vector tables
- 3. What is an Embedded System ● An embedded system is computer system designed for specific control functions ● Embedded systems contain either microcontrollers or digital signal processors ● Examples – Digital Watches, Calculaters, MP3 Players, Digital Cameras, Avionics etc
- 4. Characteristics of an Embedded System ● Cost effective ● Reliable ● Safety ● Real time critical ● Limitations against General Purpose Computers – Memory – Power consumption – Response time
- 5. Components of an Embedded System ● Hardware – Hardware specific to a specific task – Constraints regarding power consumption ● Software – Software that drives the hardware – Constriants regarding memory usage, execution time etc
- 6. Microprocessor, Microcomputer and Micorcontroller ● The microprocessor is a digital integrated circuit device that can be programmed with a series of instructions to perform specified functions on data ● A microcomputer is a microprocessor with memory device ● A microcontroller is a microprocessor with memory as well as other peripheral devices
- 7. RISC Vs CISC Pipelining is ComplexInstructions are pipelinable Small Register BankLarge Register bank Memory values can be used as operands in instructions Load/Store Architecture Several formats of instructionsFew formats of instructions Variable length instructionsFixed width instructions CISCRISC
- 8. RISC Vs CISC Compiler Processor Code Generation Greater Complexity CISC Compiler Processor Code Generation Greater Complexity RISC
- 9. ARM History ● ARM – Acorn RISC Machine(1983–1985) – Acorn Computers Limited, Cambridge, England ● ARM – Advanced RISC Machine 1990 – ARM Limited, 1990 – ARM has been licensed to many semiconductor manufacturers
- 10. ARM History ● Key component of many 32 – bit embedded systems ● Portable Consumer devices ● ARM1 prototype in 1985 ● One of the ARM’s most successful cores is the ARM7TDMI, provides high code density and low power consumption ● ARM is Physical hardware design company ● ARM licenses its cores out and other companies make processors based on its cores
- 11. Companies licensing with ARM ● 3com ● Agilent Technologies ● Altera ● Epson ● Freescale ● Fijitsu ● NEC ● Nokia ● Intel ● IBM ● Microsoft • Motorola • Panasonic • Qualcomm • Sharp • Sanyo • Sun Microsystems • Sony • Symbian • Texas Instruments • Toshiba • Wipro
- 12. ARM Cortex-M3 Register Set
- 13. ARM Cortex-M3 Register Set ● Registers – Registers: R0-R15 ● R0-R12: General Purpose Registers ● R13: The Stack Pointer ● R14: The Link Register ● R15: The Program Counter – Special Registers ● Program Status Registers ● Interrupt Mask Registers ● Control Register
- 14. Registers: R0-R15 ● R0-R12: General Purpose Registers – All are 32 bits registers – Stores data or address – Divided into two subsets ● General Purpose Registers: R0-R7 – Also called Low Registers – Accessible by all 16-bit Thumb and all 32-bit Thumb-2 Instructions ● General Purpose Registers: R8-R12 – Also called High Registers – Accessible by some 16-bit Thumb and all 32-bit Thumb-2 Instructions
- 15. Registers: R0-R15 (cont..) ● R13: The Stack Pointer (SP) – Has two banked 32-bit Stack Pointers ● Main Stack Pointer (MSP) or SP_main ● Process Stack Pointer (PSP) or SP_process – Allows two different separate stack memories to be set up – Register R13 allows to access the current Stack Pointer ● Note: Banked – Only one is visible at a time.
- 16. Registers: R0-R15 (cont..) ● Main Stack Pointer (MSP) or SP_main – Default Stack Pointer after power up – Used by code that requires privileged access – Ex. Exception Handler ● Process Stack Pointer (PSP) or SP_process – Used by code that does not require privileged access – Base-level application code
- 17. Cortex-M3 Stack model ● Cortex-M3 Stack model ● When and why to use Stack ● PUSH and POP Operations ● PUSH and POP Operations are word alligned and thus bits 0 and 1 of SP are hardwired to 0
- 18. Registers: R0-R15 (cont..) ● R14: The Link Register – Used to store the return address when subroutine or function is called – Bit 0 of Link Register indicates ARM/Thumb state – Ex.
- 19. Registers: R0-R15 (cont..) ● R15: The Program Counter ● Points to the instruction to be executed ● Because of pipeline, value inside PC is normally different than the address of executing instruction (2 – 4 bytes ahead) ● Writing to PC causes branching to the location ● Bit 0 of Program Counter indicates ARM/Thumb state
- 20. Special Registers ● Program Status Registers ● Subdivided into three status registers – Application Program Status Registers (APSR) – Interrupt Program Status Registers (IPSR) – Execution Program Status Registers (EPSR) ● Interrupt PSR and Execution PSR are read only ● All the PSRs can be accessed together or seperately ● Combined PSR is named as xPSR and while accessing use name PSR ● Requires special register access instructions (MSR and MRS)
- 23. Special Registers (cont..) ● Interrupt Mask Registers – PRIMASK – FAULTMASK – BASEPRI ● Used to disable exceptions and interrupts ● PRIMASK and BASEPRI are used for temporarily disabling interrupts in timing-critical tasks ● FAULTMASK is used for temporarily disabling fault handling when a task has crashed (fault conditions)
- 25. Special Registers (cont..) ● In Assembly language MRS and MSR instructions are used to access these registers ● A number of functions are also provided in the device driver libraries
- 26. Special Registers (cont..) ● The Control Register ● Used to define privilege level and SP selection ● Has only 2 bits – CONTROL[1] – CONTROL[0]
- 27. Special Registers (cont..) – CONTROL[1] ● Gives the stack status ● It is always 0 in handler mode ● Either 0 or 1 in thread/base level ● Writable when the core is in thread mode and privileged level ● Writing to this bit is not allowed in user state and handler mode
- 28. Special Registers (cont..) – CONTROL[0] ● Gives the mode status ● This bit is writable only in privileged state ● To change this bit when in user state, triger an interrupt and change this in exception handler
- 30. Special Registers (cont..) – Accessing the CONTROL register ● In C, CMSIS functions are available in device driver libraries – X = __get_CONTROL(); – __set_CONTROL(x); ● In Assembly MRS and MSR instructions are used – MRS R0, CONTROL – MSR CONTROL, R0
- 31. Special Registers (cont..) – Accessing the CONTROL register ● In C, CMSIS functions are available in device driver libraries – X = __get_CONTROL(); – __set_CONTROL(x); ● In Assembly MRS and MSR instructions are used – MRS R0, CONTROL – MSR CONTROL, R0
- 32. Operation Modes – Cortex M3 supports two modes and two access levels – Modes ● Handler Mode ● Thread Mode – Access Levels ● Privileged Level ● User Level
- 33. Operation Modes – Handler Mode ● Processer running in handler mode can be with privileged level
- 34. Operation Modes – Thread Mode ● Processor running in Thread mode can be with privileged as well as user access level ● After reset processor is in thread mode with privileged access level
- 35. Operation Modes – Privileged Access Level ● Can access System Control Space (SCS) which is a part of memory region for configuration registers and debubbing components ● Can access special register access instructions (MSR and MRS) ● Software in this access level can switch into user access level using control register ● On Exception, processor always switch to privileged state and return to previous state
- 36. Operation Modes – User Access Level ● Access to System Control Space is blocked ● Cannot access special register access instructions (MSR and MRS) ● Software in this access level cannot switch into privileged access level directly ● Software can switch into privileged level from exception handler
- 37. Operation Modes
- 38. Exception and Interrupts – Supports large number of exceptions and interrupts
- 39. Vector Tables – Used to determine the starting address of an exception handler – The vector table in Cortex-M3 is relocatable which is controlled by relocation register in NVIC – After reset the relocation register is reset to 0 and vector table is located at address 0x00000000 – Location 0x00000000 stores the starting value for Main Stack Pointer – LSB of the exception indicates whether the exception is the executed in Thumb state
- 40. Vector Tables
- 41. Thank you