Basic Computer Architecture and the Case for GPUs : NOTES
Computer architectures are facing issues: Memory latencies are far higher. Benefits from instruction level parallelism (ILP) is reducing. With increasing clock rates, power consumption is increasing. Increasing complexity with multi-stage pipelines, intermediate buffers, multi-level caches, out-of-order execution, branch prediction, ... GPUs are parallel computer architectures that are good at some tasks, not so good at others. Running routines with high arithmetic intensity with overlapped memory access is the preferred approach. They may be unsuitable for irregular algorithms, where it is difficult to get high efficiency due to the high latency of accesses. They are less versatile compared to CPUs, using SIMD parallelism, and are dense compute-wise (per currency). NVIDIA's CUDA programming model enables GPUs to be used for general-purpose computing, and hence the term GPGPU. GPU Architectural, Programming, and Performance Models presentation at PPoPP, 2010, Bangalore, India. By Prof. Kishore Kothapalli with Prof. P. J. Narayanan and Suryakant Patidar. https://gist.github.com/wolfram77/43a6660121eef45b78c10d4e652dad6c
Basic Computer Architecture and the Case for GPUs : NOTES
- 1. PPoPP 2010, Bangalore, India. Basic Architecture Concepts CPU Architecture 4 stages of instruction execution Too many cycles per instruction (CPI) Fetch Decode Execute Write t=1 2 3 4 5
- 2. PPoPP 2010, Bangalore, India. Basic Architecture Concepts CPU Architecture 4 stages of instruction execution Too many cycles per instruction (CPI) To reduce the CPI, introduce pipelined execution Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write t=1 2 3 4 5
- 3. PPoPP 2010, Bangalore, India. Basic Architecture Concepts CPU Architecture 4 stages of instruction execution Too many cycles per instruction (CPI) To reduce the CPI, introduce pipelined execution Needs buffers to store results across stages. A cache to handle slow memory access times Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write t=1 2 3 4 5 Cache
- 4. PPoPP 2010, Bangalore, India. Basic Architecture Concepts Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write t=1 2 3 4 5 Cache CPU Architecture 4 stages of instruction execution Too many cycles per instruction (CPI) To reduce the CPI, introduce pipelined execution Needs buffers to store results across stages. A cache to handle slow memory access times Multilevel caches, outoforder execution, branch prediction, ...
- 6. PPoPP 2010, Bangalore, India. Basic Architecture Concepts Couple with this the new wisdom in computer architectures. Memory Wall – memory latencies far higher ILP Wall – Reducing benefits from instruction level parallelism Power Wall – Increase in power consumption with increase in clock rates. Multicore is the way forward Ex: GPUs, Cell, Intel Quad core, ... Predicted that 100+ core computers would be a reality soon.