![Write sequence
1. Send a start sequence
2. Send the I2C address of the slave with the R/W
bit low (even address)
3. Send the internal register number you want to
write to
4. Send the data byte
5. [Optionally, send any further data bytes]
6. Send the stop sequence.
01.11.2020 20](https://image.slidesharecdn.com/in5350h2011io-240709205649-8252a860/85/CMOS-Image-Sensor-Design_00h20_11_io-pdf-20-320.jpg)
CMOS Image Sensor Design_00h20_11_io.pdf
- 1. IN5350 – CMOS Image Sensor Design Lecture 11 – CIS communication interfaces 27-October-2020
- 2. Project schedule Task/milestone Start Finish Chose topic/scope 1-Sep 8-Sep Create project plan (tasks, milestones, schedule) 8-Sep 15-Sep MS1 – project plan approved by Johannes 15-Sep 22-Sep Study literature on the topic 22-Sep 29-Sep Design/simulation 29-Sep 13-Oct Write up prelim report (inc references, design, results) 13-Oct 20-Oct MS2 – submit preliminary report to Johannes 20-Oct 20-Oct Design/simulation 20-Oct 27-Oct Write up final report (incl references, design, results) 27-Oct 3-Nov MS3 – presentation and discussion 3-Nov 3-Nov MS4 – submit final report to Johannes 10-Nov 10-Nov Exam 18-Nov 2020 01.11.2020 IN5350 2 ✅ ✅ ✅ ✅ ✅ ✅ ✅ ✅
- 3. Goal for this lecture • Learn how the image sensor chip communciates with host CPU using industry standard interfaces • Learn how I2C is used to write commands to the CMOS image sensor and to read register contents • Learn about pros and cons of outputing pixel data with parallel and serial interfaces 01/11/2020 3
- 4. Package types 01.11.2020 4 Ref: Harris et al, CMOS VLSI Design, 4th Ed.
- 5. Camera HW examples 01.11.2020 5 Sensor eval board FPGA + USB board DSLR camera
- 6. Sensor eval board example 01.11.2020 6 Example CIS chip
- 7. Digital input pads 01.11.2020 7 Ref: Harris et al, CMOS VLSI Design, 4th Ed. (next slide)
- 8. ESD protection 01.11.2020 8 Ref: Harris et al, CMOS VLSI Design, 4th Ed.
- 9. Bidirectional pads 01.11.2020 9 Ref: Harris et al, CMOS VLSI Design, 4th Ed.
- 10. VDDIO power dissipation 01.11.2020 10 Energy per transition (delivered by VDDIO): EIO = Cload x VDDIO 2 Power delivered to output clock pin: PCLK = Cload x VDDIO 2 x fCLK Power delivered to output pins: PIOpin = Cload x VDDIO 2 x fCLK/2 Total power: PIO = Cload x VDDIO 2 x fCLK x (1 + NDVP/2) Example: PIO=20pF (3.3V)2 100MHz (1+12/2) = 152mW(!)
- 11. Noise concern when DVP data toggles • Current in I/O pins during LOW to HIGH transition – IVDDIO = Cload dVVDDIO/dT – Typical pin load: Cload = 15pF – HDTV (720p60) output clock frequency: fCLK = 74.25MHz (74.25Mpix/sec), i.e. Cycle time of 13.5ns – Assume VDDIO=1.8V and rise time of ¼ cycle time – IVDDIO = 15pF 1.8V/(13.5ns/4) = 8mA – Assuming 0 to 1 transition on 12bit pixel value + clk • 8mA/pin x (12+1)pins = 104mA (large current spikes on VDDIO!) 01.11.2020 11
- 12. Industry trend from parallel to serial output • Driven by the megapixel raze – E.g. 8MP 30fps => 240Mpix/sec • CMOS DVP i/os limited to approx 100MHz • Adding multiple DVPs could increase die size (cost) • Driven by power and noise concerns – Current spikes in I/Os inducing supply and gnd noise • Driven by EMC requirements – Reduced EM radiation from serial interfaces w/differential signalling 01.11.2020 12
- 13. Example EMC test of digital VDD supply 01.11.2020 13
- 14. Example EMC test of digital VDD supply 01.11.2020 14
- 15. Low Voltage Differential Signaling 01.11.2020 15 Ref: National Semiconductor, LVDS owners manual.
- 16. LVDS remarks • Data rate >5Gbps per lane (1Gbps is typical) • Unaffected by common mode noise thanks to differential signalling • At 2.5V supply voltage the power to drive 3.5 mA becomes 8.75 mW per lane • Variations of LVDS for reduced power – sub-LVDS (introduced by Nokia in 2004) uses 0.9V typical common mode voltage – SLVS-400 specified in JEDEC where the power supply can be 800 mV and common mode voltage 400mV – MIPI D-PHY uses 200mV differential signalling 01.11.2020 16
- 17. I2C Inter-Integrated Circuit 01.11.2020 17 VDDIO • One device is Master, the others are Slaves (max 127) • Only the Master drives the clock line (SCL) • Pull-up resistors, Rp, typically 1.8kohms to 10kohms • Speed grades: 100kHz, 400kHz, 1MHz, 3.3MHz Master Slave Slave
- 18. Start and stop sequence and data transmission 01.11.2020 18 Data transmission: 8b data followed by 1b acknowledge from slave (i.e. SDA is pulled down by the slave device)
- 19. Addresssing an I2C device 01.11.2020 19 • 7-bit device address, i.e. max 127 devices can be connected to the bus • R/W bit informs slave that master wants to Read (‘1’) or Write (‘0’)
- 20. Write sequence 1. Send a start sequence 2. Send the I2C address of the slave with the R/W bit low (even address) 3. Send the internal register number you want to write to 4. Send the data byte 5. [Optionally, send any further data bytes] 6. Send the stop sequence. 01.11.2020 20
- 21. Read sequence 1. Send a start sequence 2. Send 0x<device address> 3. Send 0x<register address> 4. Send a start sequence again (repeated start) 5. Send 0x<device address> 6. Read data byte from device 7. Send the stop sequence 01.11.2020 21
- 22. Example read sequence 01.11.2020 22 NB. If slave is not ready for register read it can hold the SCL line low. This is called clock stretching. The master issues the first clock pulse of the read by making SCL high and then checks to see if it really has gone high. If its still low then it waits until it goes high before continuing. Example code: http://www.robot-electronics.co.uk/acatalog/I2C_Tutorial.html
- 23. Key takeaways • Digital I/O pads with level shifting and ESD protection • Parallel outputs can be power hungry – PIO = Cload x VDDIO 2 x fCLK x (1 + NDVP/2) • Industry trend from parallel to serial output (e.g. LVDS) due to higher datarates and lower EMC • I2C: industry strandard protocol used to read/write 8b values to CMOS sensor (e.g. Integration time, gain, etc) 01.11.2020 23