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Computer Architecture: ARITHMETIC FOR COMPUTERS

Gunasundari Selvaraj, profile picture
Gunasundari Selvaraj

The document provides a syllabus for a computer architecture course, focusing on arithmetic for computers including addition, subtraction, multiplication, and division along with a discussion of floating-point representation. It outlines different number representations, such as sign-and-magnitude, 1's complement, and 2's complement, and explains binary arithmetic operations like addition and subtraction, along with overflow conditions. Additionally, the document describes multiplication methods including the shift-add algorithm and Booth's algorithm for signed multiplication.

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Velammal Engineering College Department of Computer Science and Engineering Welcome…
Subject Code / Name: 19IT202T / Computer Architecture
Syllabus – Unit II UNIT-II ARITHMETIC FOR COMPUTERS Addition and Subtraction – Multiplication – Division – Floating Point Representation – Floating Point Addition and Subtraction.
Text Books • Book 1: o Name: Computer Organization and Design: The Hardware/Software Interface o Authors: David A. Patterson and John L. Hennessy o Publisher: Morgan Kaufmann / Elsevier o Edition: Fifth Edition, 2014 • Book 2: o Name: Computer Organization and Embedded Systems Interface o Authors: Carl Hamacher, Zvonko Vranesic, Safwat Zaky and Naraig Manjikian o Publisher: Tata McGraw Hill o Edition: Sixth Edition, 2012
• numbers may be represented in any base • Computer - base 2 numbers are called binary numbers • A single digit of a binary number is the “atom” of computing, since all information is composed of binary digits or bit. • Alternatives: high or low, on or off , true or false, or 1 or 0 • Least Significant Bit(LSB): The rightmost bit in a MIPS word. • Most Significant Bit(MSB): The left most bit in a MIPS word. Numbers
The Binary Number System • Name o “binarius” (Latin) => two • Characteristics o Two symbols • 0 1 o Positional • 1010B ≠ 1100B • Most (digital) computers use the binary number system Terminology • •Bit: a binary digit • •Byte: (typically) 8 bits
Number Representation • Three systems: o Sign-and-magnitude o 1’s complement o 2’s complement • In all three systems, the leftmost bit is 0 for positive numbers and 1 for negative numbers. • Positive values have identical representations in all systems. • Negative values have different representations. • Ex: 10112
• Sign Magnitude: One's Complement Two's Complement 000 = 0 000 = 0 000 = 0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = 0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = 0 111 = -1 • Issues: o balance – equal number of negatives and positives o ambiguous zero – whether more than one zero representation o ease of arithmetic operations • Which representation is best? Can we get both balance and non-ambiguous zero? Possible Representations ambiguous zero ambiguous zero
Signed Magnitude • In this notation, an extra bit is added to the left of the number to notate its sign. • 0 indicates +ve and 1 indicates -ve. • Using 8 bits, • +13 is 00001101 and +11 is 00001011. • -13 is 10001101 and -11 is 10001011.
1's Complement • In this notation positive numbers are represented exactly as regular binary numbers. • Negative numbers are represented simply by flipping the bit, i.e. 0's become 1 and 1's become 0. • So 13 will be 00001101 and 11 will be 00001011. • -13 will be 11110010 and -11 will be 11110100.
2's Complement • In this method a negative number is notated by first determining the 1's complement of the positive number and then adding 1 to it. • So 8-bit -13 will be 11110010 • (1's complement) + 1 = 11110011; • -11 will be 11110101.
Question • Find the 2’s-complement of 1011010? • 0100110
• 32 bit signed numbers: 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten 0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten 0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten ... 0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten 0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten 1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten ... 1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten 1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten 1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten MIPS – 2’s complement maxint minint Negative integers are exactly those that have leftmost bit 1
Binary Addition
Binary Addition • 710 + 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610
Binary Addition • 710 + 610 0000 0000 0000 0000 0000 0000 0000 011 1 2 = 710 0000 0000 0000 0000 0000 0000 0000 011 0 2 = 610 1 2
Binary Addition • 710 + 610 1 0000 0000 0000 0000 0000 0000 0000 01 1 12 = 710 0000 0000 0000 0000 0000 0000 0000 01 1 02 = 610 12 0
Binary Addition • 710 + 610 1 0000 0000 0000 0000 0000 0000 0000 0 1 112 = 710 0000 0000 0000 0000 0000 0000 0000 0 1 102 = 610 012 1 1
Binary Addition • 710 + 610 1 1 0000 0000 0000 0000 0000 0000 0000 0 1112 = 710 0000 0000 0000 0000 0000 0000 0000 0 1102 = 610 1012 1
Binary Addition • 710 + 610 11 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 11012
Binary Addition • 710 + 610 11 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 11012 = 1310
Binary Subtraction
Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610
Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 011 1 2 = 710 0000 0000 0000 0000 0000 0000 0000 011 0 2 = 610 1
Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01 1 12 = 710 0000 0000 0000 0000 0000 0000 0000 01 1 02 = 610 1 0
Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 0 1 112 = 710 0000 0000 0000 0000 0000 0000 0000 0 1 102 = 610 0 01
Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 00012
Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 00012 = 110
Binary Subtraction • 2’s Complement Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 2’s c of - 610=1111 1111 1111 1111 1111 1111 1111 10102 = 610 0000 0000 0000 0000 0000 0000 0000 00012 = 110
Example • When adding or subtracting 2's complement binary numbers, any extra (carry over) bits are discarded. • 13–11 • 13 + (-11) • 00001101 + 11110101 • 100000010
Overflow • When the actual result of an arithmetic operation is outside the representable range, an arithmetic overflow has occurred. • No overflow when adding a positive and a negative number • No overflow when subtracting numbers with the same sign • Overflow occurs when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result.
Overflow
Overflow - Example • No overflow when adding a positive and a negative number • A+B • A = +3 • B = -2 +3 => 011 -2 => 110 • ----------- +1 => 001 • Result - representable range n=3 bits => Range: - 4 to +3 +3 011 +2 010 +1 001 0 000 -1 111 -2 110 -3 101 -4 100
Overflow - Example • No overflow when subtracting numbers with the same sign • A - B • A = - 3 • B = - 2 • (-3) – (-2) => -3 + 2 -3 => 101 +2 => 010 • ----------- -1 => 111 • Result - representable range n=3 bits => Range: - 4 to +3 +3 011 +2 010 +1 001 0 000 -1 111 -2 110 -3 101 -4 100
Overflow - Example • Overflow occurs when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result. • A + B • A = + 3 • B = + 3 +3 => 011 +3 => 011 • ----------- -2 => 110 X n=3 bits => Range: - 4 to +3 +3 011 +2 010 +1 001 0 000 -1 111 -2 110 -3 101 -4 100
• No overflow when adding a positive and a negative number • No overflow when subtracting numbers with the same sign • Overflow occurs when the result has “wrong” sign (verify!): Operation Operand A Operand B Result Indicating Overflow A + B  0  0  0 A + B  0  0  0 A – B  0  0  0 A – B  0  0  0 • Consider the operations A + B, and A – B o can overflow occur if B is 0 ? o can overflow occur if A is 0 ? Detecting Overflow
Questions 1. Subtract (11010)2 – (10000)2 using 2’s complement method. 2. Subtract (11011)2 – (10011)2 using 2’s complement. Solution:
Questions 1. Add −8 to +3 2. Add −5 to −2 use 8-bit two’s complement numbers Solution: (+3) 0000 0011 +(−8) 1111 1000 ----------------- (−5) 1111 1011 (−2) 1111 1110 +(−5) 1111 1011 ----------------- (−7) 1 1111 1001 : discard carry-out
Multiply • Grade school shift-add method: Multiplicand 1000 Multiplier 1001 x 1000 0000 0000 1000 Product 01001000 • m bits x n bits = m+n bit product • Binary makes it easy: o multiplier bit 1 => copy multiplicand (1 x multiplicand) o multiplier bit 0 => place 0 (0 x multiplicand) x Intermediate products
Sequential Version of the Multiplication Algorithm and Hardware 64-bit ALU Control test Multiplier Shift right Product Write Multiplicand Shift left 64 bits 64 bits 32 bits Done 1. Test Multiplier0 1a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit 32nd repetition? Start Multiplier0 = 0 Multiplier0 = 1 No: < 32 repetitions Yes: 32 repetitions Multiplicand register, product register, ALU are 64-bit wide; multiplier register is 32-bit wide Algorithm 32-bit multiplicand starts at right half of multiplicand register Product register is initialized at 0 Hardware
Sequential Version of the Multiplication Algorithm and Hardware • Basic 3 steps: 1. if LSB multiplier ==1 Product = Product + Multiplicand else No operation 2. Shift the multiplicand left 3. Shift the multiplier right These three steps are repeated 32 times.
Shift-add Multiplier Itera Step Multiplier Multiplicand Product -tion 0 init 0011 0000 0010 0000 0000 values 1 1a 0011 0000 0010 0000 0010 2 0011 0000 0100 0000 0010 3 0001 0000 0100 0000 0010 2 1a 0001 0000 0100 0000 0110 2 0001 0000 1000 0000 0110 3 0000 0000 1000 0000 0110 3 1 0000 0000 1000 0000 0110 2 0000 0001 0000 0000 0110 3 0000 0001 0000 0000 0110 4 1 0000 0001 0000 0000 0110 2 0000 0010 0000 0000 0110 3 0000 0010 0000 0000 0110 Example: 0010 * 0011: Algorithm Done 1. Test Multiplier0 1a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit 32nd repetition? Start Multiplier0 = 0 Multiplier0 = 1 No: < 32 repetitions Yes: 32 repetitions Final Product
Multiplication Exercises • 1) 13 * 11 • 2) 7 * 5
Signed Multiplication Booth Algorithm The Booth Algorithm: • The Booth algorithm generates a 2n-bit product and treats both positive and negative 2’scomplement n-bit operands uniformly. • The Booth algorithm has two attractive features. First, it handles both positive and negative multipliers uniformly. Second, it achieves some efficiency in the number of additions required when the multiplier has a few large blocks of 1s.
Signed Multiplication Booth Algorithm Booth multiplier recoding table
Booth Algorithm Booth Recoded Multipliers Ex: -6 -6 in 2’s complement is 11010 11010 0 Peform recoding 1 1 0 1 0 0 Add a zero to the RHS of the multiplier 0 -1 +1 -1 So this is the recoded multiplier 0
Questions • Find the Booth recoded multiplier for the given numbers: 1. -14 2. -5 3. -12
Booth Multiplication • Let us perform +13 * -6 Steps: • Recode the multiplier -6 when recoded is 0 -1 +1 -1 0 +13 = 0 1 1 0 1 - 6 = 0-1+1-10 Note: Multiplier bit is : 0 All 0s +1 multiplicand -1 2’s c of multiplicand 0 1 1 0 1 X 0-1+1-10 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 Final Product = 11101100102 = -7810 Carry is ignored
Normal and Booth multiplication
1001 Quotient Divisor 1000 1001010 Dividend –1000 10 101 1010 –1000 10 Remainder • Junior school method: see how big a multiple of the divisor can be subtracted, creating quotient digit at each step • Binary makes it easy  first, try 1 * divisor; if too big, 0 * divisor • Dividend = (Quotient * Divisor) + Remainder Division
Restoring Division 64-bit ALU Control test Quotient Shift left Remainder Write Divisor Shift right 64 bits 64 bits 32 bits Done Test Remainder 2a. Shift the Quotient register to the left, setting the new rightmost bit to 1 3. Shift the Divisor register right 1 bit 33rd repetition? Start Remainder < 0 No: < 33 repetitions Yes: 33 repetitions 2b. Restore the original value by adding the Divisor register to the Remainder register and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder > 0 – Divisor register, remainder register, ALU are 64-bit wide; quotient register is 32-bit wide Algorithm 32-bit divisor starts at left half of divisor register Remainder register is initialized with the dividend at right Why 33? We shall see later… Quotient register is initialized to be 0
Division Done Test Remainder 2a. Shift the Quotient register to the left, setting the new rightmost bit to 1 3. Shift the Divisor register right 1 bit 33rd repetition? Start Remainder < 0 No: < 33 repetitions Yes: 33 repetitions 2b. Restore the original value by adding the Divisor register to the Remainder register and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder > 0 – Itera- Step Quotient Divisor Remainder tion 0 init 0000 0010 0000 0000 0111 1 1 0000 0010 0000 1110 0111 2b 0000 0010 0000 0000 0111 3 0000 0001 0000 0000 0111 2 1 0000 0001 0000 1111 0111 2b 0000 0001 0000 0000 0111 3 0000 0000 1000 0000 0111 3 1 0000 0000 1000 1111 1111 2b 0000 0000 1000 0000 0111 3 0000 0000 0100 0000 0111 4 1 0000 0000 0100 0000 0011 2a 0001 0000 0100 0000 0011 3 0001 0000 0010 0000 0011 5 1 0001 0000 0010 0000 0001 2a 0011 0000 0010 0000 0001 3 0011 0000 0001 0000 0001 Example: 0111 / 0010: Algorithm R = Reminder – Divisor R = 0000 0111 – 0010 0000 R = 1110 0111 Restore, R = R + D R = Reminder – Divisor R = 0000 0111 – 0001 0000 R = 1111 0111 Restore, R = R + D R = Reminder – Divisor R = 0000 0111 – 0000 1000 R = 1111 1111 Restore, R = R + D R = Reminder – Divisor R = 0000 0111 – 0000 0100 R = 0000 0011 R = Reminder – Divisor R = 0000 0011 – 0000 0010 R = 0000 0001
Signed Division • Remainder = Dividend - (Quotient · Divisor) • Four cases:
Division Exercises • 13 / 5 • 6 / 2
Floating Point Representation
Floating Point • We need a way to represent o numbers with fractions, e.g., 3.1416 o very small numbers (in absolute value), e.g., .00000000023 o very large numbers (in absolute value) , e.g., – 3.15576 * 1046
Floating Point • Scientific Notation: o A notation that renders numbers with a single digit to the left of the decimal point. o Ex: 1.0 X 10-9 o 3.15576 X 109 • Normalized Number: o A number in floating point notation that has no leading 0s. o Ex: 1.0 X 10-9 o 1.0 X 2-1 • Binary form: 1.xxxxxx X 2yyyy
Exercise Change the following binary numbers into normalized number: Hint: a single non-zero digit to the left of the binary point. Binary Value Normalized Value 10000.11 1.000011 x 24 10.0 × 2-9 (0.010101)2×24 .0000011001 10000011.0 .00101
Floating Point Representation • IEEE 754 floating point standard: o single precision: one word o double precision: two words 31 sign bits 30 to 23 8-bit exponent bits 22 to 0 23-bit fraction 31 sign bits 30 to 20 11-bit exponent bits 19 to 0 upper 20 bits of 52-bit fraction bits 31 to 0 lower 32 bits of 52-bit fraction
Floating Point Representation • Sign bit o The sign of a binary floating-point number is represented by a single bit. o A 1 bit indicates a negative number, and a 0 bit indicates a positive number. • Fraction: o The value, generally between 0 and 1, placed in the fraction field. The fraction is also called the mantissa. • Exponent: o In the numerical representation system of floating-point arithmetic, the value that is placed in the exponent field. • Example: +1.10101 x 25 Sign bit = 0 (positive) Fraction = .10101 Exponent = 5
Floating Point • Still use a fixed number of bits o Sign bit S, exponent E, significand F o Value: (-1)S x (1+F) x 2E • IEEE 754 standard 6 1 Size Sign bit Exponent Fraction or Significand Range Single precision 32b 1b 8b 23b 2x10+/-38 Double precision 64b 1b 11b 52b 2x10+/-308 S E F
Biased Exponent • A biased exponent is the result of adding some constant(called the bias) to the exponent to make the range of the exponent nonnegative. • Biased exponent = Exponent + bias • Bias = 2n-1 – 1 • Single : 127 , Double : 1023 • Example: 1.101 x 25 Biased Exponent = 5 + 127 =132 (1000 0100) • Example: 1.01001 x 2-3 Biased Exponent = -3 + 127 =124 (0111 1100)
Exercise Exponent (E) Biased exponent (E + 127) Binary Representation 5 +162 10100010 0 -10 127 -1
Excess or Biased Exponent • Value: (-1)S x (1 + F) x 2(E-bias) o SP: bias is 127 o DP: bias is 1023 6 4 Exponent 2’s Compl Excess-127 -127 1000 0001 0000 0000 -126 1000 0010 0000 0001 … … … +127 0111 1111 1111 1110
FP Overflow/Underflow • FP Overflow o Analogous to integer overflow o Result is too big to represent o Means exponent is too big • FP Underflow o Result is too small to represent o Means exponent is too small (too negative) • Both can raise an exception under IEEE754 6 5
IEEE754 Special Cases 6 6 Single Precision Double Precision Value Exponent Significand Exponent Significand 0 0 0 0 0 0 nonzero 0 nonzero denormalized 1-254 anything 1-2046 anything fp number 255 0 2047 0 infinity 255 nonzero 2047 nonzero NaN (Not a Number)
Show the IEEE 754 binary representation of the number -0.75ten in single and double precision Converting -0.75ten to binary 0.75 x 2 = 1.50 (take only integral part, ie 1) 0.50 x 2 = 1.00 0.11 x 2 0 After Normalizing the above value is 1.1 x 2 -1 The general representation for a single precision no is (-1)S x (1 + F) x 2(E-127) Subtracting the bias 127 from the exponent of -1.1two x 2-1 yields (-1)1 x (1+.1000 0000 0000 0000 0000 000two) x 2(126-127) (Contd…)
(Contd…) The single precision binary representation of -0.75ten is then The double precision representation is Show the IEEE 754 binary representation of the number -0.75ten in single and double precision
Exercise • Represent the following numbers in Single and Double precision formats. 1. +.0000001101011 2. -.00101
Exercise • What decimal number is represented by this single precision float?
Exercise • Assuming single precision IEEE 754 format, what decimal number is represent by this word? 1 01111101 00100000000000000000000
Floating Point Addition • Binary floating point addition: • Steps: 1. Compare the exponents of the two numbers; shift the smaller number to the right until its exponent would match the larger exponent 2. Add the significands 3. Normalize the sum, either shifting right and incrementing the exponent or shifting left and decrementing the exponent 4. Round the significand to the appropriate number of bits
Floating Point Addition/Subtraction
Floating Point Addition/Subtraction
Floating Point Addition/Subtraction
Thank You

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Computer Architecture: ARITHMETIC FOR COMPUTERS

  • 1. Velammal Engineering College Department of Computer Science and Engineering Welcome…
  • 2. Subject Code / Name: 19IT202T / Computer Architecture
  • 3. Syllabus – Unit II UNIT-II ARITHMETIC FOR COMPUTERS Addition and Subtraction – Multiplication – Division – Floating Point Representation – Floating Point Addition and Subtraction.
  • 4. Text Books • Book 1: o Name: Computer Organization and Design: The Hardware/Software Interface o Authors: David A. Patterson and John L. Hennessy o Publisher: Morgan Kaufmann / Elsevier o Edition: Fifth Edition, 2014 • Book 2: o Name: Computer Organization and Embedded Systems Interface o Authors: Carl Hamacher, Zvonko Vranesic, Safwat Zaky and Naraig Manjikian o Publisher: Tata McGraw Hill o Edition: Sixth Edition, 2012
  • 5. • numbers may be represented in any base • Computer - base 2 numbers are called binary numbers • A single digit of a binary number is the “atom” of computing, since all information is composed of binary digits or bit. • Alternatives: high or low, on or off , true or false, or 1 or 0 • Least Significant Bit(LSB): The rightmost bit in a MIPS word. • Most Significant Bit(MSB): The left most bit in a MIPS word. Numbers
  • 6. The Binary Number System • Name o “binarius” (Latin) => two • Characteristics o Two symbols • 0 1 o Positional • 1010B ≠ 1100B • Most (digital) computers use the binary number system Terminology • •Bit: a binary digit • •Byte: (typically) 8 bits
  • 7. Number Representation • Three systems: o Sign-and-magnitude o 1’s complement o 2’s complement • In all three systems, the leftmost bit is 0 for positive numbers and 1 for negative numbers. • Positive values have identical representations in all systems. • Negative values have different representations. • Ex: 10112
  • 8. • Sign Magnitude: One's Complement Two's Complement 000 = 0 000 = 0 000 = 0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = 0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = 0 111 = -1 • Issues: o balance – equal number of negatives and positives o ambiguous zero – whether more than one zero representation o ease of arithmetic operations • Which representation is best? Can we get both balance and non-ambiguous zero? Possible Representations ambiguous zero ambiguous zero
  • 9. Signed Magnitude • In this notation, an extra bit is added to the left of the number to notate its sign. • 0 indicates +ve and 1 indicates -ve. • Using 8 bits, • +13 is 00001101 and +11 is 00001011. • -13 is 10001101 and -11 is 10001011.
  • 10. 1's Complement • In this notation positive numbers are represented exactly as regular binary numbers. • Negative numbers are represented simply by flipping the bit, i.e. 0's become 1 and 1's become 0. • So 13 will be 00001101 and 11 will be 00001011. • -13 will be 11110010 and -11 will be 11110100.
  • 11. 2's Complement • In this method a negative number is notated by first determining the 1's complement of the positive number and then adding 1 to it. • So 8-bit -13 will be 11110010 • (1's complement) + 1 = 11110011; • -11 will be 11110101.
  • 12. Question • Find the 2’s-complement of 1011010? • 0100110
  • 13. • 32 bit signed numbers: 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten 0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten 0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten ... 0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten 0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten 1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten 1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten ... 1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten 1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten 1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten MIPS – 2’s complement maxint minint Negative integers are exactly those that have leftmost bit 1
  • 15. Binary Addition • 710 + 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610
  • 16. Binary Addition • 710 + 610 0000 0000 0000 0000 0000 0000 0000 011 1 2 = 710 0000 0000 0000 0000 0000 0000 0000 011 0 2 = 610 1 2
  • 17. Binary Addition • 710 + 610 1 0000 0000 0000 0000 0000 0000 0000 01 1 12 = 710 0000 0000 0000 0000 0000 0000 0000 01 1 02 = 610 12 0
  • 18. Binary Addition • 710 + 610 1 0000 0000 0000 0000 0000 0000 0000 0 1 112 = 710 0000 0000 0000 0000 0000 0000 0000 0 1 102 = 610 012 1 1
  • 19. Binary Addition • 710 + 610 1 1 0000 0000 0000 0000 0000 0000 0000 0 1112 = 710 0000 0000 0000 0000 0000 0000 0000 0 1102 = 610 1012 1
  • 20. Binary Addition • 710 + 610 11 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 11012
  • 21. Binary Addition • 710 + 610 11 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 11012 = 1310
  • 23. Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610
  • 24. Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 011 1 2 = 710 0000 0000 0000 0000 0000 0000 0000 011 0 2 = 610 1
  • 25. Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01 1 12 = 710 0000 0000 0000 0000 0000 0000 0000 01 1 02 = 610 1 0
  • 26. Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 0 1 112 = 710 0000 0000 0000 0000 0000 0000 0000 0 1 102 = 610 0 01
  • 27. Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 00012
  • 28. Binary Subtraction • Direct Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 0000 0000 0000 0000 0000 0000 0000 01102 = 610 0000 0000 0000 0000 0000 0000 0000 00012 = 110
  • 29. Binary Subtraction • 2’s Complement Method 710 - 610 0000 0000 0000 0000 0000 0000 0000 01112 = 710 2’s c of - 610=1111 1111 1111 1111 1111 1111 1111 10102 = 610 0000 0000 0000 0000 0000 0000 0000 00012 = 110
  • 30. Example • When adding or subtracting 2's complement binary numbers, any extra (carry over) bits are discarded. • 13–11 • 13 + (-11) • 00001101 + 11110101 • 100000010
  • 31. Overflow • When the actual result of an arithmetic operation is outside the representable range, an arithmetic overflow has occurred. • No overflow when adding a positive and a negative number • No overflow when subtracting numbers with the same sign • Overflow occurs when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result.
  • 33. Overflow - Example • No overflow when adding a positive and a negative number • A+B • A = +3 • B = -2 +3 => 011 -2 => 110 • ----------- +1 => 001 • Result - representable range n=3 bits => Range: - 4 to +3 +3 011 +2 010 +1 001 0 000 -1 111 -2 110 -3 101 -4 100
  • 34. Overflow - Example • No overflow when subtracting numbers with the same sign • A - B • A = - 3 • B = - 2 • (-3) – (-2) => -3 + 2 -3 => 101 +2 => 010 • ----------- -1 => 111 • Result - representable range n=3 bits => Range: - 4 to +3 +3 011 +2 010 +1 001 0 000 -1 111 -2 110 -3 101 -4 100
  • 35. Overflow - Example • Overflow occurs when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result. • A + B • A = + 3 • B = + 3 +3 => 011 +3 => 011 • ----------- -2 => 110 X n=3 bits => Range: - 4 to +3 +3 011 +2 010 +1 001 0 000 -1 111 -2 110 -3 101 -4 100
  • 36. • No overflow when adding a positive and a negative number • No overflow when subtracting numbers with the same sign • Overflow occurs when the result has “wrong” sign (verify!): Operation Operand A Operand B Result Indicating Overflow A + B  0  0  0 A + B  0  0  0 A – B  0  0  0 A – B  0  0  0 • Consider the operations A + B, and A – B o can overflow occur if B is 0 ? o can overflow occur if A is 0 ? Detecting Overflow
  • 37. Questions 1. Subtract (11010)2 – (10000)2 using 2’s complement method. 2. Subtract (11011)2 – (10011)2 using 2’s complement. Solution:
  • 38. Questions 1. Add −8 to +3 2. Add −5 to −2 use 8-bit two’s complement numbers Solution: (+3) 0000 0011 +(−8) 1111 1000 ----------------- (−5) 1111 1011 (−2) 1111 1110 +(−5) 1111 1011 ----------------- (−7) 1 1111 1001 : discard carry-out
  • 39. Multiply • Grade school shift-add method: Multiplicand 1000 Multiplier 1001 x 1000 0000 0000 1000 Product 01001000 • m bits x n bits = m+n bit product • Binary makes it easy: o multiplier bit 1 => copy multiplicand (1 x multiplicand) o multiplier bit 0 => place 0 (0 x multiplicand) x Intermediate products
  • 40. Sequential Version of the Multiplication Algorithm and Hardware 64-bit ALU Control test Multiplier Shift right Product Write Multiplicand Shift left 64 bits 64 bits 32 bits Done 1. Test Multiplier0 1a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit 32nd repetition? Start Multiplier0 = 0 Multiplier0 = 1 No: < 32 repetitions Yes: 32 repetitions Multiplicand register, product register, ALU are 64-bit wide; multiplier register is 32-bit wide Algorithm 32-bit multiplicand starts at right half of multiplicand register Product register is initialized at 0 Hardware
  • 41. Sequential Version of the Multiplication Algorithm and Hardware • Basic 3 steps: 1. if LSB multiplier ==1 Product = Product + Multiplicand else No operation 2. Shift the multiplicand left 3. Shift the multiplier right These three steps are repeated 32 times.
  • 42. Shift-add Multiplier Itera Step Multiplier Multiplicand Product -tion 0 init 0011 0000 0010 0000 0000 values 1 1a 0011 0000 0010 0000 0010 2 0011 0000 0100 0000 0010 3 0001 0000 0100 0000 0010 2 1a 0001 0000 0100 0000 0110 2 0001 0000 1000 0000 0110 3 0000 0000 1000 0000 0110 3 1 0000 0000 1000 0000 0110 2 0000 0001 0000 0000 0110 3 0000 0001 0000 0000 0110 4 1 0000 0001 0000 0000 0110 2 0000 0010 0000 0000 0110 3 0000 0010 0000 0000 0110 Example: 0010 * 0011: Algorithm Done 1. Test Multiplier0 1a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit 32nd repetition? Start Multiplier0 = 0 Multiplier0 = 1 No: < 32 repetitions Yes: 32 repetitions Final Product
  • 43. Multiplication Exercises • 1) 13 * 11 • 2) 7 * 5
  • 44. Signed Multiplication Booth Algorithm The Booth Algorithm: • The Booth algorithm generates a 2n-bit product and treats both positive and negative 2’scomplement n-bit operands uniformly. • The Booth algorithm has two attractive features. First, it handles both positive and negative multipliers uniformly. Second, it achieves some efficiency in the number of additions required when the multiplier has a few large blocks of 1s.
  • 45. Signed Multiplication Booth Algorithm Booth multiplier recoding table
  • 46. Booth Algorithm Booth Recoded Multipliers Ex: -6 -6 in 2’s complement is 11010 11010 0 Peform recoding 1 1 0 1 0 0 Add a zero to the RHS of the multiplier 0 -1 +1 -1 So this is the recoded multiplier 0
  • 47. Questions • Find the Booth recoded multiplier for the given numbers: 1. -14 2. -5 3. -12
  • 48. Booth Multiplication • Let us perform +13 * -6 Steps: • Recode the multiplier -6 when recoded is 0 -1 +1 -1 0 +13 = 0 1 1 0 1 - 6 = 0-1+1-10 Note: Multiplier bit is : 0 All 0s +1 multiplicand -1 2’s c of multiplicand 0 1 1 0 1 X 0-1+1-10 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 Final Product = 11101100102 = -7810 Carry is ignored
  • 49. Normal and Booth multiplication
  • 50. 1001 Quotient Divisor 1000 1001010 Dividend –1000 10 101 1010 –1000 10 Remainder • Junior school method: see how big a multiple of the divisor can be subtracted, creating quotient digit at each step • Binary makes it easy  first, try 1 * divisor; if too big, 0 * divisor • Dividend = (Quotient * Divisor) + Remainder Division
  • 51. Restoring Division 64-bit ALU Control test Quotient Shift left Remainder Write Divisor Shift right 64 bits 64 bits 32 bits Done Test Remainder 2a. Shift the Quotient register to the left, setting the new rightmost bit to 1 3. Shift the Divisor register right 1 bit 33rd repetition? Start Remainder < 0 No: < 33 repetitions Yes: 33 repetitions 2b. Restore the original value by adding the Divisor register to the Remainder register and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder > 0 – Divisor register, remainder register, ALU are 64-bit wide; quotient register is 32-bit wide Algorithm 32-bit divisor starts at left half of divisor register Remainder register is initialized with the dividend at right Why 33? We shall see later… Quotient register is initialized to be 0
  • 52. Division Done Test Remainder 2a. Shift the Quotient register to the left, setting the new rightmost bit to 1 3. Shift the Divisor register right 1 bit 33rd repetition? Start Remainder < 0 No: < 33 repetitions Yes: 33 repetitions 2b. Restore the original value by adding the Divisor register to the Remainder register and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder > 0 – Itera- Step Quotient Divisor Remainder tion 0 init 0000 0010 0000 0000 0111 1 1 0000 0010 0000 1110 0111 2b 0000 0010 0000 0000 0111 3 0000 0001 0000 0000 0111 2 1 0000 0001 0000 1111 0111 2b 0000 0001 0000 0000 0111 3 0000 0000 1000 0000 0111 3 1 0000 0000 1000 1111 1111 2b 0000 0000 1000 0000 0111 3 0000 0000 0100 0000 0111 4 1 0000 0000 0100 0000 0011 2a 0001 0000 0100 0000 0011 3 0001 0000 0010 0000 0011 5 1 0001 0000 0010 0000 0001 2a 0011 0000 0010 0000 0001 3 0011 0000 0001 0000 0001 Example: 0111 / 0010: Algorithm R = Reminder – Divisor R = 0000 0111 – 0010 0000 R = 1110 0111 Restore, R = R + D R = Reminder – Divisor R = 0000 0111 – 0001 0000 R = 1111 0111 Restore, R = R + D R = Reminder – Divisor R = 0000 0111 – 0000 1000 R = 1111 1111 Restore, R = R + D R = Reminder – Divisor R = 0000 0111 – 0000 0100 R = 0000 0011 R = Reminder – Divisor R = 0000 0011 – 0000 0010 R = 0000 0001
  • 53. Signed Division • Remainder = Dividend - (Quotient · Divisor) • Four cases:
  • 54. Division Exercises • 13 / 5 • 6 / 2
  • 56. Floating Point • We need a way to represent o numbers with fractions, e.g., 3.1416 o very small numbers (in absolute value), e.g., .00000000023 o very large numbers (in absolute value) , e.g., – 3.15576 * 1046
  • 57. Floating Point • Scientific Notation: o A notation that renders numbers with a single digit to the left of the decimal point. o Ex: 1.0 X 10-9 o 3.15576 X 109 • Normalized Number: o A number in floating point notation that has no leading 0s. o Ex: 1.0 X 10-9 o 1.0 X 2-1 • Binary form: 1.xxxxxx X 2yyyy
  • 58. Exercise Change the following binary numbers into normalized number: Hint: a single non-zero digit to the left of the binary point. Binary Value Normalized Value 10000.11 1.000011 x 24 10.0 × 2-9 (0.010101)2×24 .0000011001 10000011.0 .00101
  • 59. Floating Point Representation • IEEE 754 floating point standard: o single precision: one word o double precision: two words 31 sign bits 30 to 23 8-bit exponent bits 22 to 0 23-bit fraction 31 sign bits 30 to 20 11-bit exponent bits 19 to 0 upper 20 bits of 52-bit fraction bits 31 to 0 lower 32 bits of 52-bit fraction
  • 60. Floating Point Representation • Sign bit o The sign of a binary floating-point number is represented by a single bit. o A 1 bit indicates a negative number, and a 0 bit indicates a positive number. • Fraction: o The value, generally between 0 and 1, placed in the fraction field. The fraction is also called the mantissa. • Exponent: o In the numerical representation system of floating-point arithmetic, the value that is placed in the exponent field. • Example: +1.10101 x 25 Sign bit = 0 (positive) Fraction = .10101 Exponent = 5
  • 61. Floating Point • Still use a fixed number of bits o Sign bit S, exponent E, significand F o Value: (-1)S x (1+F) x 2E • IEEE 754 standard 6 1 Size Sign bit Exponent Fraction or Significand Range Single precision 32b 1b 8b 23b 2x10+/-38 Double precision 64b 1b 11b 52b 2x10+/-308 S E F
  • 62. Biased Exponent • A biased exponent is the result of adding some constant(called the bias) to the exponent to make the range of the exponent nonnegative. • Biased exponent = Exponent + bias • Bias = 2n-1 – 1 • Single : 127 , Double : 1023 • Example: 1.101 x 25 Biased Exponent = 5 + 127 =132 (1000 0100) • Example: 1.01001 x 2-3 Biased Exponent = -3 + 127 =124 (0111 1100)
  • 63. Exercise Exponent (E) Biased exponent (E + 127) Binary Representation 5 +162 10100010 0 -10 127 -1
  • 64. Excess or Biased Exponent • Value: (-1)S x (1 + F) x 2(E-bias) o SP: bias is 127 o DP: bias is 1023 6 4 Exponent 2’s Compl Excess-127 -127 1000 0001 0000 0000 -126 1000 0010 0000 0001 … … … +127 0111 1111 1111 1110
  • 65. FP Overflow/Underflow • FP Overflow o Analogous to integer overflow o Result is too big to represent o Means exponent is too big • FP Underflow o Result is too small to represent o Means exponent is too small (too negative) • Both can raise an exception under IEEE754 6 5
  • 66. IEEE754 Special Cases 6 6 Single Precision Double Precision Value Exponent Significand Exponent Significand 0 0 0 0 0 0 nonzero 0 nonzero denormalized 1-254 anything 1-2046 anything fp number 255 0 2047 0 infinity 255 nonzero 2047 nonzero NaN (Not a Number)
  • 67. Show the IEEE 754 binary representation of the number -0.75ten in single and double precision Converting -0.75ten to binary 0.75 x 2 = 1.50 (take only integral part, ie 1) 0.50 x 2 = 1.00 0.11 x 2 0 After Normalizing the above value is 1.1 x 2 -1 The general representation for a single precision no is (-1)S x (1 + F) x 2(E-127) Subtracting the bias 127 from the exponent of -1.1two x 2-1 yields (-1)1 x (1+.1000 0000 0000 0000 0000 000two) x 2(126-127) (Contd…)
  • 68. (Contd…) The single precision binary representation of -0.75ten is then The double precision representation is Show the IEEE 754 binary representation of the number -0.75ten in single and double precision
  • 69. Exercise • Represent the following numbers in Single and Double precision formats. 1. +.0000001101011 2. -.00101
  • 70. Exercise • What decimal number is represented by this single precision float?
  • 71. Exercise • Assuming single precision IEEE 754 format, what decimal number is represent by this word? 1 01111101 00100000000000000000000
  • 72. Floating Point Addition • Binary floating point addition: • Steps: 1. Compare the exponents of the two numbers; shift the smaller number to the right until its exponent would match the larger exponent 2. Add the significands 3. Normalize the sum, either shifting right and incrementing the exponent or shifting left and decrementing the exponent 4. Round the significand to the appropriate number of bits