Computer Architecture - Data Path & Pipeline Hazards
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The document provides a detailed overview of MIPS architecture, including instruction formats, major functional units, and data path constructions. It explains the various instruction types (R-type, I-type, J-type) and their execution steps, along with pipelining techniques and the handling of pipeline hazards such as structural and data hazards. Additionally, it covers solutions to mitigate these hazards and enhance processing efficiency.
![06-10-2021 11
Dr. K.K. THYAGHARAJAN
Read
Address
Instr[31-0]
Instruction
Memory
Add
1
P
C
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data
1
Read
Data
2
ALU
ovf
zero
RegWrite
Data
Memory
Address
Write Data
Read
Data
MemWrite
MemRead
Sign
Extend
16 32
ALUSrc
Shift
left 2
Add
2
PCSrc =0
RegDst
ALU
Control
1
1
0
0 0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25 -21]
Instr[20 -16]
Instr[15 -
11]
Control
Unit
Instr [31 -26]
Branch = 0
MemtoReg
1
0 next instruction
1 jump inst.
0- R Inst.
1 – I Inst.
for sw
0- R Inst.
1 – I Inst.
1- R type
0- lw
rd
rt
rs
MemRead
Instruction RegDst ALUSrc MemtoReg RegWrite MemR
add $t1, $t2, $t3 1 0 0 1 0
next instruction
Example:
add $t1, $t2, $t3
funct
31 25 20 15 5 0
op rs=t2 rt=t3 rd=t1 shamt
10
R-type:
Control Lines are in
Yellow colour
Data path is in red colour](https://image.slidesharecdn.com/caounit3-211006164703/85/Computer-Architecture-Data-Path-Pipeline-Hazards-9-320.jpg)
![06-10-2021 13
Dr. K.K. THYAGHARAJAN
Read
Address Instr[31-0]
Instruction
Memory
Add
1
P
C
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data 1
Read
Data 2
ALU
ovf
zero
RegWrite
Data
Memory
Address
Write Data
Read
Data
MemWrite
MemRead
Sign
Extend
16 32
ALUSrc
Shift
left 2
Add
2
PCSrc
RegDst
ALU
Control
1
1
0
0 0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25 -21]
Instr[20 -16]
Instr[15 -
11]
Control
Unit
Instr [31 -26]
Branch = 0
MemtoReg
1
0 next instruction
1 jump inst.
0- R Inst.
1 – I Inst.
for sw
0- R Inst.
1 – I Inst.
1- R type
0- lw
rd
rt
rs
MemRead
Instruction RegDst ALUSrc MemtoReg RegWrite MemR
add $t1, $t2, $t3 0 1 1 1 1
next instruction
Example:
lw $t1 100($t2)
Control Lines are in
Yellow colour
Data path is in red colour
address offset /data
op rs =$t2 rt=$t1
31 25 20 15 0](https://image.slidesharecdn.com/caounit3-211006164703/85/Computer-Architecture-Data-Path-Pipeline-Hazards-11-320.jpg)
Computer Architecture - Data Path & Pipeline Hazards
- 1. 06-10-2021 1 Dr. K.K. THYAGHARAJAN Computer Architecture and Organization UNIT 3 Dr. K.K. THYAGHARAJAN
- 2. 06-10-2021 2 Dr. K.K. THYAGHARAJAN MIPS Instructions to be Recalled address offset /data funct op rs rt 31 25 20 15 0 31 25 20 15 5 0 op rs rt rd shamt 10 31 25 0 op target address I-Type: R-type: J-type: add $s1,$s2,$s3 lw $t1, 100 ($s0) ; sw $s1, 20($s2) beq $s1,$t1,100 PC+4 + (25*4) j 2500 addi $s1,$s2,5 For MIPS Architecture design, the instructions are divided into three classes The memory reference instructions load word (lw) and store word (sw) The arithmetic logical instructions add, sub, AND, OR, and slt The branch instructions branch equal (beq) and jump (j)
- 3. 06-10-2021 3 Dr. K.K. THYAGHARAJAN MIPS: Major functional units and interconnections between them Program counter gives the address of the Instruction. The instruction is fetched from Instruction memory. Decoded to get the address of the registers and the data is read from these registers. The values read from registers are given to ALU for execution (add, sub etc.). The result obtained from ALU is written on the data memory or on the destination register.
- 4. 06-10-2021 4 Dr. K.K. THYAGHARAJAN beq $s1,$t1,100 Address in the instruction = 100 x4 Target address = PC +4 + Address in the instruction Structure of the Datapath segment that handles branches
- 5. 06-10-2021 5 Dr. K.K. THYAGHARAJAN The simple Datapath for the core MIPS architecture RegWrite add $s1,$s2,$s3 MemtoReg ALUSrc addi $s1,$s2,20 lw $s1, 20($s2) ALUSrc MemRead MemtoReg RegWrite beq $s1, $s2, 25 --- PC+4 + (25*4) PCSrc
- 6. 06-10-2021 6 Dr. K.K. THYAGHARAJAN lw $s1, 20($s2) sw $s1, 20($s2) beq $s1, $s2, 25 add $s1,$s2,$s3 sub $s1,$s2,$s3 and $s1,$s2,$s3 or $s1,$s2,$s3 ALU op Function 00 Load or Store 01 Branch 10 R-type
- 7. 06-10-2021 7 Dr. K.K. THYAGHARAJAN The Datapath with control unit
- 8. 06-10-2021 10 Dr. K.K. THYAGHARAJAN Question1: Explain the steps in constructing the Datapath with control lines for R-type MIPS instruction with neat diagram. Example : add $t1, $t2, $t3 Step 1: The instruction is fetched, and the PC is incremented. Step 2: Two registers, $t2 and $t3, are read from the register file; also, the main control unit computes the setting of the control lines during this step. Step 3: The ALU operates on the data read from the register file, using the function code (bits 5:0, which is the funct field, of the instruction) to generate the ALU function. Step 4: The result from the ALU is written into the register file using bits 15:11 of the instruction to select the destination register ($t1). funct 31 25 20 15 5 0 op rs rt rd shamt 10 R-type:
- 9. 06-10-2021 11 Dr. K.K. THYAGHARAJAN Read Address Instr[31-0] Instruction Memory Add 1 P C 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 ALUSrc Shift left 2 Add 2 PCSrc =0 RegDst ALU Control 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25 -21] Instr[20 -16] Instr[15 - 11] Control Unit Instr [31 -26] Branch = 0 MemtoReg 1 0 next instruction 1 jump inst. 0- R Inst. 1 – I Inst. for sw 0- R Inst. 1 – I Inst. 1- R type 0- lw rd rt rs MemRead Instruction RegDst ALUSrc MemtoReg RegWrite MemR add $t1, $t2, $t3 1 0 0 1 0 next instruction Example: add $t1, $t2, $t3 funct 31 25 20 15 5 0 op rs=t2 rt=t3 rd=t1 shamt 10 R-type: Control Lines are in Yellow colour Data path is in red colour
- 10. 06-10-2021 12 Dr. K.K. THYAGHARAJAN Question1: Draw and explain the Datapath connection with control lines for the instruction lw $t1 100($t2) address offset /data op rs rt 31 25 20 15 0 Step 1: An instruction is fetched from the instruction memory, and the PC is incremented Step 2: A register ($t2) value is read from the register file Step 3: The ALU computes the sum of the value read from the register file and the sign extended, lower 16 bits of the instruction (offset) Step 4: The sum from the ALU is used as the address for the data memory Step 5: The data from the memory unit is written into the register file the register destination is given by bits 20:16 of the instruction ($t1)
- 11. 06-10-2021 13 Dr. K.K. THYAGHARAJAN Read Address Instr[31-0] Instruction Memory Add 1 P C 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 ALUSrc Shift left 2 Add 2 PCSrc RegDst ALU Control 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25 -21] Instr[20 -16] Instr[15 - 11] Control Unit Instr [31 -26] Branch = 0 MemtoReg 1 0 next instruction 1 jump inst. 0- R Inst. 1 – I Inst. for sw 0- R Inst. 1 – I Inst. 1- R type 0- lw rd rt rs MemRead Instruction RegDst ALUSrc MemtoReg RegWrite MemR add $t1, $t2, $t3 0 1 1 1 1 next instruction Example: lw $t1 100($t2) Control Lines are in Yellow colour Data path is in red colour address offset /data op rs =$t2 rt=$t1 31 25 20 15 0
- 12. 06-10-2021 14 Dr. K.K. THYAGHARAJAN Assignment 1. Draw and explain the datapath connection with control lines for the instruction beq $s1,$s2,100 2. Explain the steps in constructing the datapath with control lines for load word MIPS instruction with neat diagram.
- 13. 06-10-2021 15 Dr. K.K. THYAGHARAJAN Pipelining
- 14. 06-10-2021 16 Dr. K.K. THYAGHARAJAN Pipelining Pipelining is an implementation technique in which multiple instructions are overlapped in execution. The stages of instruction execution / pipelining are 1. IF: Instruction fetch 2. ID: Instruction decode and Register read 3. EX: Execution or address calculation (ALU Operation) 4. MEM: Data memory access 5. WB: Write back (Register Write) ps Pico second
- 15. 06-10-2021 17 Dr. K.K. THYAGHARAJAN Non-Pipelined Execution Pipelined Execution
- 16. 06-10-2021 19 Dr. K.K. THYAGHARAJAN Data Path With Pipeline Stages Data flow is from left to right except for the PC-next value and write back the result to register file (Blue Colour) Data flowing from right to left does not affect the current instruction. The first right to left flow of data can lead to data hazards and the second leads to control hazards
- 17. 06-10-2021 20 Dr. K.K. THYAGHARAJAN PIPELINED DATAPATH WITH THE PIPELINE REGISTERS All instructions advance during each clock cycle from one pipeline register to the next The registers must be wide enough to store all the data corresponding to the lines that go through them IF/ID register must be 64 bits wide, because it must hold both the 32 bit instruction fetched from memory and the incremented 32 bit PC address
- 18. 06-10-2021 21 Dr. K.K. THYAGHARAJAN Draw and explain the pipelined data path for executing lw $s1,100 ($s0) instruction is read from memory using the address in the PC (Program Counter) and then placed in the IF/ID pipeline register The PC is incremented by 4 and then written into the PC to be ready for the next clock cycle. This incremented address is also saved in the IF/ID pipeline register in case it is needed later for an instruction, such as beq The computer cannot know which type of instruction is being fetched, so it must prepare for any instruction, passing potentially needed information down the pipeline
- 19. 06-10-2021 22 Dr. K.K. THYAGHARAJAN Draw and explain the pipelined data path for executing lw $s1,100 ($s0) All three values are stored in the ID/EX pipeline register. Although the load needs only the top register in stage 2, the processor doesn’t know what instruction is being decoded, so it sign extends the 16 bit constant and reads both registers into the ID/EX pipeline register
- 20. 06-10-2021 23 Dr. K.K. THYAGHARAJAN the load instruction reads the contents of register 1 and the sign extended immediate from the ID/EX pipeline register and adds them using the ALU That sum is placed in the EX/MEM pipeline register Draw and explain the pipelined data path for executing lw $s1,100 ($s0)
- 21. 06-10-2021 24 Dr. K.K. THYAGHARAJAN load instruction reads the data memory using the address from the EX/MEM pipeline register and loads the data into the MEM/WB pipeline register Draw and explain the pipelined data path for executing lw $s1,100 ($s0)
- 22. 06-10-2021 25 Dr. K.K. THYAGHARAJAN Reads the data from the MEM/WB pipeline register and writes it into the register file
- 23. 06-10-2021 26 Dr. K.K. THYAGHARAJAN Pipeline Datapath with Control Lines
- 24. 06-10-2021 27 Dr. K.K. THYAGHARAJAN
- 25. 06-10-2021 28 Dr. K.K. THYAGHARAJAN Hazards: situations that makes the pipeline to stall or idle. 1. Structural hazards – Caused by resource contention – Using same resource by two instructions during the same cycle 2. Data hazards – An instruction may compute a result needed by next instruction – Hardware can detect dependencies between instructions 3. Control hazards – Caused by instructions that change control flow (branches/jumps) – Delays in changing the flow of control • Hazards complicate pipeline control and limit performance Pipeline Hazards
- 26. 06-10-2021 29 Dr. K.K. THYAGHARAJAN Cycle 1 Reg ALU Ifetch Reg Reg ALU DMem Ifetch Reg Reg ALU DMem Ifetch Reg Reg ALU DMem Ifetch Reg Reg ALU DMem Ifetch Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Can’t load data and fetch Instruction 4 during the same clock cycle (4) Structural Hazard - Conflict due to Memory Access Time Load lw $s1, 100($s0) Instr 2 Instr 3 Instr 4 add $s1,$s2,$s3 Instr 5 Same memory is used for instructions and data ID/Ex DMem Right highlight – Read Operation Left highlight – Write Operation Blank (back ground Colour) – Not used – Bypass line IF/ID Ex/MEM MEM/WB
- 27. 06-10-2021 30 Dr. K.K. THYAGHARAJAN Problem Two different instructions attempt to use the same hardware resource (Memory) during the same cycle • Solution 1: Introduce a delay (stall) before the second instruction access the resource using bubble / NOP • Solution 2: Redesign the pipeline Add more hardware to eliminate the structural hazard In our example, use separate memory for Instructions and Data. Actually we are using separate memories in our previous discussions Resolving structural hazards
- 28. 06-10-2021 32 Dr. K.K. THYAGHARAJAN Cycle 1 Reg ALU Ifetch Reg Reg ALU Ifetch Reg Reg ALU Ifetch Reg Reg ALU DMem Ifetch Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Structural Hazard - Conflict due to Memory Access Time Load lw $1, 100($0) Instr 2 Instr 3 Instr 4 add $1,$2,$3 Reg ALU DMem Ifetch Reg Instr 5 ID/Reg Stall Insert a bubble to delay the instruction fetching Bubble Bubble Bubble Bubble Bubble Bubble is a NOP Instruction DMem DMem DMem
- 29. 06-10-2021 33 Dr. K.K. THYAGHARAJAN 1. Read After Write – RAW Hazard I: add $s1, $s2, $s3 # s1 is written J: sub $s4, $s1, $s3 # s1 is read Instruction J should read an operand after it is written by I Hazard occurs when J reads the operand before I writes it This happens when dependent instructions are close to each other. This is called a data dependence in compiler terminology Data Hazards
- 30. 06-10-2021 34 Dr. K.K. THYAGHARAJAN Cycle 1 Reg ALU Reg Reg ALU DM Reg Reg ALU DM Reg Reg ALU DM Ifetch Reg Reg ALU DM Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 RAW (Read After Write) Data Hazard Time sub $s2, $s1,$s3 and $s4,$s2,$s5 ID/Reg Right highlight – Read Operation Left highlight – Write Operation Blank (back ground Colour) – Not used – Bypass line IM DM or $s6,$s3,$s2 add $s7,$s2,$s2 sw $s8, 100($s2) IM IM IM IM Result of sub (i.e. $s2) is needed by and, or, add, & sw instructions Instructions and & or will read old value of $s2 from reg file During cycle 5, $s2 is written and read – new value is read
- 31. 06-10-2021 35 Dr. K.K. THYAGHARAJAN Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE a) Operand forwarding (Hardware) b) Reordering code (Software) c) By using Stall Solutions to RAW data hazard
- 32. 06-10-2021 36 Dr. K.K. THYAGHARAJAN Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE a. Operand Forwarding (Forwarding ALU Result) The ALU result is forwarded (fed back) to the ALU input No bubbles are inserted into the pipeline and no cycles are wasted ALU result exists in either EX/MEM or MEM/WB register Cycle 1 Reg ALU Reg Reg ALU DM Reg Reg ALU DM Reg Reg ALU DM Ifetch Reg Reg ALU DM Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Time sub $s2, $s1,$s3 and $s4,$s2,$s5 ID/Reg IM DM or $s6,$s3,$s2 add $s7,$s2,$s2 sw $s8, 100($s2) IM IM IM IM
- 33. 06-10-2021 37 Dr. K.K. THYAGHARAJAN Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE ALU and pipeline registers after adding forwarding
- 34. 06-10-2021 38 Dr. K.K. THYAGHARAJAN Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE b. Reordering the Code to Solve Data Hazard Cycle 1 Reg ALU Reg Reg ALU DM Reg Reg ALU DM Reg Reg ALU Ifetch Reg Reg ALU Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Time lw $t1, 0(t0) lw $t2, 4($t0) ID/Reg IM add $t3,$t1,$s2 sw $t3, 12($t0) lw $t4, 8($to) IM IM IM IM DM add $t5, $t1, $t4 DM DM Reg ALU DM Reg IM The order of the instructions may be changed such that one instruction need not wait for the other instruction’s result without affecting the logic This add instructions have a hazard. t1 for adding from 1st lw is not available until 5th clock cycle This add instructions have a hazard. t4 for adding from 3rd lw is not available until 10th clock cycle
- 35. 06-10-2021 39 Dr. K.K. THYAGHARAJAN Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE b. Reordering the Code to Solve Data Hazard Cycle 1 Reg ALU Reg Reg ALU DM Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Time lw $t1, 0(t0) lw $t2, 4($t0) ID/Reg IM IM DM add $t5, $t1, $t4 add $t3,$t1,$s2 sw $t3, 12($t0) ALU Reg DM Reg IM Reg ALU Ifetch Reg IM DM lw $t4, 8($to) Reg ALU Reg IM DM Reg ALU DM Reg IM Now $t1 register is available for reading at clock cycle 5 Now $t4 register is available for reading at clock cycle 7
- 36. 06-10-2021 40 Dr. K.K. THYAGHARAJAN Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $s2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) Both add instructions have a hazard t1 and t2 are not available for add from 1st lw until 5th clock cycle lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $s2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) Reordered instructions Both add instructions have a hazard
- 37. 06-10-2021 41 Dr. K.K. THYAGHARAJAN Cycle 1 Reg ALU Reg Reg ALU DM Reg Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Stalling the Pipeline Time sub $s2, $s1,$s3 and $s4,$s2,$s5 IM DM or $s6,$s3,$s2 Reg ALU DM Reg IM IM The and instruction cannot fetch $s2 until cycle 5 Two bubbles (NOP instructions) are inserted in ID/EX at the end of Cycle 3 and Cycle 4 ID/Ex IF/ID Ex/MEM MEM/WB ALU DM Reg ALU DM Reg Bubble Bubble Bubble $s2 is not available. So, introduce a bubble $s2 is still not available. So, introduce one more bubble
- 38. 06-10-2021 42 Dr. K.K. THYAGHARAJAN