Counit2
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1. The document describes the von Neumann architecture and its key components including the ALU, control unit, memory and I/O devices. 2. It explains the structure of the von Neumann machine and details the functions of components like the program counter, memory address register, and instruction register. 3. The document covers integer and floating point representation in binary, including sign-magnitude, two's complement, and IEEE 754 standard. It describes arithmetic operations like addition, subtraction, multiplication and division on binary numbers.
Counit2
- 1. Unit 2
- 2. von Neumann/Turing • Stored Program concept • Main memory storing programs and data • ALU operating on binary data • Control unit interpreting instructions from memory and executing • Input and output equipment operated by control unit • Princeton Institute for Advanced Studies —IAS • Completed 1952
- 3. Structure of von Neumann machine
- 4. • Structure of IAS – detail
- 5. • MemoryAddressRegister(MAR)-This register holds the address of the memory location to be accessed. The desired address is loaded into MAR through a common Bus. • ProgramCounter(PC)-This register keeps track of the program flow. Its count is incremented after every fetch of Op Code or Operand from the Program Memory. • StackPointer(SP)-This is an up down counter which holds the address of the top of the Stack. Its count is incremented or decremented after every Push or Pop operation of the Stack. • InstructionRegister(IR)- The OpCode fetched from the program memory is loaded here, and its output is fed to the Instruction Decoder for generating the Control Signals. • TemporaryRegisters-These registers are accessible only to the system,and cannot be accessed by the user.
- 8. Arithmetic & Logic Unit • Does the calculations • Everything else in the computer is there to service this unit • Handles integers • May handle floating point (real) numbers • May be separate FPU (maths co- processor) • May be on chip separate FPU (486DX +)
- 10. ALU Inputs and Outputs
- 11. Integer Representation • Only have 0 & 1 to represent everything • Positive numbers stored in binary —e.g. 41=00101001 • No minus sign • No period • Sign-Magnitude • Two’s compliment
- 12. Sign-Magnitude • Left most bit is sign bit (MSB) • 0 means positive • 1 means negative • +18 = 00010010 • -18 = 10010010 • Problems —Need to consider both sign and magnitude in arithmetic —Two representations of zero (+0 and -0)
- 13. Two’s Compliment • +3 = 00000011 • +2 = 00000010 • +1 = 00000001 • +0 = 00000000 • -1 = 11111111 • -2 = 11111110 • -3 = 11111101
- 14. Benefits • One representation of zero • Arithmetic works easily (see later) • Negating is fairly easy —3 = 00000011 —Boolean complement gives 11111100 —Add 1 to LSB 11111101
- 15. Geometric Depiction of Twos Complement Integers
- 16. Negation Special Case 1 • 0= 00000000 • Bitwise not 11111111 • Add 1 to LSB +1 • Result 1 00000000 • There is carry out of MSB which is ignored , so: • -0=0
- 17. Negation Special Case 2 • -128 = 10000000 • bitwise not 01111111 • Add 1 to LSB +1 • Result 10000000 • So: • -(-128) = -128 X • Monitor MSB (sign bit) • It should change during negation
- 18. Range of Numbers • 8 bit 2s compliment —+127 = 01111111 = 27 -1 — -128 = 10000000 = -27 • 16 bit 2s compliment —+32767 = 011111111 11111111 = 215 - 1 — -32768 = 100000000 00000000 = -215
- 19. Conversion Between Lengths • Positive number pack with leading zeros • +18 = 00010010 • +18 = 00000000 00010010 • Negative numbers pack with leading ones • -18 = 10010010 • -18 = 11111111 10010010 • i.e. pack with MSB (sign bit)
- 20. Addition and Subtraction • Normal binary addition • Monitor sign bit for overflow • Take twos compliment of subtrahend and add to minuend —i.e. a - b = a + (-b) • So we only need addition and complement circuits
- 23. • If the two numbers are added and they are both positive or both negative number, then overflow occurs if the result has the opposite sign.
- 24. Hardware for Addition and Subtraction
- 25. Multiplication • Complex • Work out partial product for each digit • Take care with place value (column) • Add partial products
- 26. Multiplication Example • 1011 Multiplicand (11 dec) • x 1101 Multiplier (13 dec) • 1011 Partial products • 0000 Note: if multiplier bit is 1 copy • 1011 multiplicand (place value) • 1011 otherwise zero • 10001111 Product (143 dec) • Note: need double length result
- 29. Flowchart for Unsigned Binary Multiplication
- 30. Multiplying Negative Numbers • This does not work! • Solution 1 —Convert to positive if required —Multiply as above —If signs were different, negate answer • Solution 2 —Booth’s algorithm
- 32. Example of Booth’s Algorithm
- 33. Division • More complex than multiplication • Negative numbers are really bad! • Based on long division
- 35. Division of Unsigned Binary Integers 00001101 Quotient Divisor 1011 10010011 Dividend 1011 001110 Partial 1011 Remainders 001111 1011 100 Remainder
- 36. Flowchart for Unsigned Binary Division
- 38. Real Numbers • Numbers with fractions • Could be done in pure binary —1001.1010 = 24 + 20 +2-1 + 2-3 =9.625 • Where is the binary point? • Fixed? —Very limited • Moving? —How do you show where it is?
- 39. Floating Point • +/- .significand x 2exponent • Misnomer • Point is actually fixed between sign bit and body of mantissa • Exponent indicates place value (point position)
- 41. Signs for Floating Point • Mantissa is stored in 2s compliment • Exponent is in excess or biased notation —e.g. Excess (bias) 128 means —8 bit exponent field —Pure value range 0-255 —Subtract 128 to get correct value —Range -128 to +127
- 42. Normalization • FP numbers are usually normalized • i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1 • Since it is always 1 there is no need to store it • (c.f. Scientific notation where numbers are normalized to give a single digit before the decimal point • e.g. 3.123 x 103)
- 43. FP Ranges • For a 32 bit number —8 bit exponent —+/- 2256 1.5 x 1077 • Accuracy —The effect of changing lsb of mantissa —23 bit mantissa 2-23 1.2 x 10-7 —About 6 decimal places
- 45. IEEE 754 • Standard for floating point storage • 32 and 64 bit standards • 8 and 11 bit exponent respectively • Extended formats (both mantissa and exponent) for intermediate results
- 46. IEEE 754 Formats
- 47. • 1. Convert the decimal number to binary. • 2. Write the binary number in scientific notation using 20 • 3. Normalise the number by moving the binary point and changing the exponent. • 4. Write f by taking the fractional part of the normalised number and adding trailing zeroes to get 23 bits. • 5. Determine sign bit. • 6. Add 127 to the exponent (from step 3) to get e. • 7. Convert e to an 8 bit binary number (add leading • zeroes if needed). • 8. Write in IEEE format by concatenating s, e, and f.
- 48. • (24.5)10 • 11000.1 • Write in scientific notation • 11000.1 x 20 • Normalise the number by moving the binary point and changing the exponent • 1.10001 x 24 • 100 0100 0000 0000 0000 0000 • Sign bit = 0 • Add 127 to get e • e=127+4=131 • Convert 131 to binary • 10000011 • 0 1000 0011 100 0100 0000 0000 0000 0000
- 49. • 1. Regroup the binary digits into groups of 1, 8, and 23 digits. • 2. Convert e to a decimal number. • 3. Subtract 127 to get the exponent . • 4. Delete the trailing zeroes from f and write 1.f x 2exponent where the exponent is the value from step 3 and f is the original f with the trailing zeroes removed. • 5. Un-normalise the number by moving the binary point until the exponent is 0. • 6. Drop the 20. It is no longer needed. • 7. Convert the binary number to decimal. • 8. If s is 1, put a minus sign in front of the decimal number.
- 50. • 1100 0001 1100 0100 0000 0000 0000 0000 • 1 1000 0011 100 0100 0000 0000 0000 0000 • Convert e to decimal • 1000 0011 = 131 • Subtract 127 to get true exponent • 131-127=4 • Delete the trailing zeroes from f and write 1.f * 2exponent. • 100 0100 0000 0000 0000 0000 • 10001 • 1.10001 x 24
- 51. • Un-normalise the number by moving and binary point until the exponent is 0. • 1.10001 x 24 = 11000.1 x 20 • 11000.1 • 24.5 • s=1 • Answer is -24.5