Design and implementation of five stage pipelined RISC-V processor using Verilog

B. Tech ECE PROJECT-1 Review-1
Design and implementation of five stage pipelined
RISC V processor using Verilog
To design and implement a 5-stage pipelined RISC-V processor in Verilog and verify it
using UVM (Universal Verification Methodology).
Team Members Details Faculty Guide
RITHISH KUMAR R S:- 21BEC2521 Dr. SAKTHIVEL R
SAKTHIVEL B:- 21BEC2165 Department:- SENSE

CURRENT STATUS AND MOTIVATION
Current status:
We have implemented a five staged 32-bit RISC V, which includes six
instruction set types : R-type ,I-type, B-type, J-type , L-type and S-type.
This design features a five-stage pipeline consisting of instruction fetch,
instruction decode, instruction execute, memory access, write back stages.
Motivation:
RISC-V is an open-source ISA, allowing for modifications and extensions to
meet specific needs, making it suitable for various applications, including
embedded systems.
The pipelined architecture enhances the operating frequency and overall
performance of the processor by allowing multiple instructions to be
processed simultaneously at different stages.

IDENTIFICATION OF GAPS IN RISC V:
RISC V despite its potential, has several gaps like its software ecosystem is
less developed compared to established architectures like ARM and x86, and
its hardware implementations are still maturing in terms of performance
and efficiency.
Ensuring that RISC-V cores comply with the ISA specifications is a
significant challenge. This includes verifying that all instructions and
registers are correctly implemented and that there are no
unexpected behaviors.
Although the RISC-V ecosystem is growing, there are still gaps in the
availability and maturity of tools, simulators, and verification methods.
Addressing these challenges is essential for RISC-V wider adoption and
success.

Software Used:
The primary development was done using Modelsim , and Quartus prime
was used to synthesis the output
Modelsim:
Primary used for simulating HDL designs (VHDL , Verilog). It helps developers
Verify and debug their hardware logic by providing detailed waveform outputs and
Simulation logs.
Quartus Prime:
This is used for synthesis, compilation, and programming of designs onto
FPGA hardware. It takes the HDL design and synthesizes it into a hardware circuit that
Can be mapped onto a programmable device.
Programming language used: Verilog

OBJECTIVE
Our primary objective is to design a 32- bit RISC V Processor using Verilog for hardware
description and to use Universal Verification Methodology(UVM) for comprehensive
verification. The key goals are:
1 Accurate Processor Design: Develop a fully functional 32-bit RISC V processor that
Implements the base integer instruction set (RV32I), supporting arithmetic, logical , contro
Flow, and memory operations.
2 Efficiency and Performance: Optimize the processor design for efficient execution of
Instructions, implementing pipelining to improve performance without sacrificing accuracy
making the design suitable for embedded and low-power low-area applications.
3 Comprehensive Verification with UVM: Develop a robust and reusable UVM-based
Testbench to verify the RISC –V processor at all levels of abstraction, ensuring complete
Functional coverage with the help of wide range test scenarios.

METHODOLOGY
Architecture of RV32I processor:
This architecture contains:
Controller Blocks
Controller pipeline
Data path Blocks
Data path pipeline
Controller
Hazard Unit
Data Memory
Instruction Memory

METHODOLOGY:
ALU ( Arithmetic Logic Unit ) :
All the Arthimetic Shift and Logic Operations are done in the R-Type Instruction set So designing
ALU for R-Type and using this for Other Type Instructions.
Let there be two 32 bit inputs and one 32 bit outputs.

ISA (Instruction Set Architecture):
Each instruction is 32 bits long and divided into several fields:
Opcode: Instruction[6:0] (determines the instruction type)
rd: Instruction[11:7] (destination register)
funct3: Instruction[14:12] (operation variant)
rs1: Instruction[19:15] (source register 1)
rs2: Instruction[24:20] (source register 2)
funct7: Instruction[31:25] (additional operation information)

Opcode:
The opcode is used to define the type of instruction to be executed:
R-Type: 0110011 (ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND)
I-Type: 0010011 (ADDI, SLLI, SLTI, SLTIU, XORI, SRLI, SRAI, ORI, ANDI)
B-Type: 1100011 (BEQ, BNE, BLTU, BGTU)
J-Type: 1101111 (JAL)
L-Type: 0000011 (LW)
S-Type: 0100011 (SW)
Immediate Fields ( Sign Extenstion) :
But some Instructions don't use this fields instead they have Immediate fields and is calculated as

Instruction Execution :
R - Type Instructions get executed as per the ALU
I - Type follows the same as ALU but I-type Does not have SUB Operation
B - Type Instruction uses SUB operation to compare values
S and L Operation uses ADD operation to calculate the Memory Address
J - type uses ADD operation to calculate Address of Register File
Control Signal :
Control Signal = {funct7,funct3}
R Type Instruction Explained :
ADD : RegFile[rd] = RegFile[rs2]+RegFile[rs1];
SUB : RegFile[rd] = RegFile[rs1]-RegFile[rs2];
SLL : RegFile[rd] = RegFile[rs1] << (RegFile[rs2] & 0x1F);
SLT : RegFile[rd] = ( (signed long)RegFile[rs1] < (signed long)RegFile[rs2] ) ? 1 : 0;
SLTU : RegFile[rd] = (RegFile[rs1]<RegFile[rs2]) ? 1 : 0;
XOR : RegFile[rd] = RegFile[rs1] ^ RegFile[rs2];
SRL : RegFile[rd] = RegFile[rs1] >> (RegFile[rs2] & 0x1F);
SRA : RegFile[rd] = RegFile[rs1] >>> (RegFile[rs2] & 0x1F);
OR : RegFile[rd] = RegFile[rs1] | RegFile[rs2];
AND : RegFile[rd] = RegFile[rs1] & RegFile[rs2];

I - Type Instruction Explained :
ADDI : RegFile[rd] = Immediate_Value+RegFile[rs1];
SLLI : RegFile[rd] = RegFile[rs1] << (Immediate_Value & 0x1F);
SLTI : RegFile[rd] = ( (signed long)RegFile[rs1] < (signed long)Immediate_Value ) ? 1 : 0;
SLTIU : RegFile[rd] = (RegFile[rs1]<Immediate_Value) ? 1 : 0;
XORI : RegFile[rd] = RegFile[rs1] ^ Immediate_Value;
SRLI : RegFile[rd] = RegFile[rs1] >> (Immediate_Value & 0x1F);
SRAI : RegFile[rd] = RegFile[rs1] >> >(Immediate_Value & 0x1F);
ORI : RegFile[rd] = RegFile[rs1] | Immediate_value;
ANDI : RegFile[rd] = RegFile[rs1] & Immediate_Value;
B - Type Instruction Explained :
BEQ : if(RegFile[rs1] == RegFile[rs2])
{ PC = Immediate_Value + PC ; }
BNE : if(RegFile[rs1] != RegFile[rs2])
BLTU : if(RegFile[rs1] < RegFile[rs2])
{ PC = Immediate_Value + PC ;}
BGTU : if(RegFile[rs1] >= RegFile[rs2])

S Type Instruction Explained :
SW : Data_Memory[(Immediate_Value + RegFile[rs1])] = RegFile[rs2] ;
J Type Instruction Explained :
JAL : RegFile[rd] = PC + 0x4; PC = Immediate_Value + PC ;
L Type Instruction Explained :
LW : RegFile[rd] = Data_Memory[Immediate_Value + RegFile[rs1]] ;
Understanding Memories :
Register File :
•These are the registers that are present inside the cpu and some are used for specific operations and some
of them are temporary registers which are used for data storage .
•RV32 has 32 Registers each 32 Bit Wide. As there are 32 Regiters, 2^5 so 5 Bits Address are required.
Instruction Memory :
•This is the memory that user writes in it each cell of this memory is 8 Bit Wide and it contains the
Instructions in order of which it gets executed
•As Program Counter holds the Address of Instruction Memory and is 32 Bit wide so maximum size of
Instruction Memory can be 2^32.
•And Output Instruction is 32 Bit Wide Considering it LITTLE ENDIAN CPU.

Data Memory :
• This can be considered as RAM because it stores the data.
•Data can be read or written from Data Memory.
• ALU result acts at its address which is 32 bit, so maximum size of Data Memory is 2^32.
Program Counter :
•Program Counter is the register which has the address of the instruction that is being executed.
• Its value increments once its instruction gets executed.
• The PC Value should change depending on JUMP and Branch Type Instructions.
Data Forwarding :
•Forwarding is a technique that is used to avoid hazards in pipelined processors.
•These occur when instruction close to each other use the same data.
•If Both the registers in the excution and memory cycle are same i.e rs1 or rs2 == rd, then we get the value
directly from ALU Result.
Stalling :
Let us consider we need to do a read operation and the cpu is doing write operation, but CPU doesn't execute
read and write at the same time So, We stop the pipeline making it repeat the instruction in the next cycle
until the issue gets cleared

RESULTS
RTL SYNTHESIS OF TOP MODULE:

RTL SYNTHESIS OF CONTROLLER BLOCK

SCOPE FOR IMPROVEMENT
The current RISC-V processor design can be enhanced to support more
advanced operations.
1)Floating-Point Arithmetic:
Floating-point units (FPU) handle operations with real numbers using a format
that supports a wide range of values, including very small and very large
numbers. FPUs use specialized hardware to perform arithmetic operations
like addition, subtraction, multiplication, and division on floating-point
numbers, offering higher precision and efficiency for complex calculations.
Improved accuracy for real number computations
2)MAC Unit (Multiply-Accumulate)
The MAC unit performs both multiplication and addition in a single instruction.
It multiplies two numbers and adds the result to an accumulator, making it ideal
for tasks involving repetitive calculations like digital signal processing (DSP) and
machine learning algorithms. Efficient handling of complex arithmetic operations

SOCIAL IMPACT
The RISC V processor project offers notable social benefits, particularly by democratizing acce
To processor technology though its open-source nature. This encourages innovation from sm
companies, startups and academic institutions, making hardware design more affordable and
accessible globally. It plays a key role in education, training future engineers and contributing
workforce development. Customizable RISC V processor have the potential to enhance sector
like health care, energy efficiency and IOT, making technology more specialized and sustainab
Moreover, RISC V promotes technology more specialized and sustainable. Moreover, RISC V
Promotes technological independence by reducing reliance on proprietary architectures,
Fostering Greater sovereignty for governments and industries. The project also supports secu
and transparency, allowing for open auditing of designs, which leads to safer, more ethical
technology development that benefits society at large.

SUSTAINABLE DEVELOPMENT GOALS
 No Poverty: Enables affordable technology for financial inclusion, such as mobile banking.
 Zero Hunger: Powers precision agriculture tools, like IoT sensors for monitoring crop
health.
 Good Health: Supports low-cost medical devices and telemedicine solutions.
 Quality Education: Facilitates affordable learning devices to improve access to digital
education.
 Gender Equality: Provides platforms that enhance access to education and financial
services for women.
 Clean Water: Implements IoT systems for monitoring and managing water quality
effectively.
 Clean Energy: Powers energy-efficient smart grids and renewable energy management
systems.
 Decent Work: Promotes the digital economy, fostering job creation and innovation.
 Sustainable Cities: Enables smart city solutions, such as traffic management and waste
optimization through IoT.
 Climate Action: Reduces the carbon footprint of technology through energy-efficient
designs.

TIME LINE (Aug. to Nov 2024)
July (20th
– 30th
):- Deciding the title of the project and started to read out research papers.
Started to implement the Blocks using Verilog.
August 1st
to September 15th
:- Learned about the architecture of RISC V and Completed the
RTL coding for RISC V processor with necessary datapaths, Hazards and stages and testbenc
for each block.
September 15th
to October 20th
:- verify the implementation using UVM.

REFERENCES
1. D. Bhandarkar and D.W. Clark, “Performance from Architecture: Comparing a RISC and a CISC with Similar
Hardware
Organization,”Proceedings of the 4th Int’l. Conference on ASPLOS, Santa Clara, California, April 8-11, 1991.
2. Kulshreshtha, A., Moudgil, A., Chaurasia, A. and Bhushan, B., 2021, March. Analysis of 16-Bit and 32-Bit RISC Processors. In
2021 7th
International Conference on Advanced Computing and Communication Systems (ICACCS) (Vol. 1, pp. 1318-1324). IEEE.
3. Khairullah, S.S., 2022, June. Realization of a 16-bit MIPS RISC pipeline processor. In 2022 International Congress on Human-
Computer.
4. M. N. Topiwala and N. Saraswathi, "Implementation of a 32-bit MIPS based RISC processor using Cadence," 2014 IEEE
International Conference on Advanced Communications, Control and Computing Technologies, 2014.
5. Islam, S., Chattopadhyay, D., Das, M.K., Neelima, V. and Sarkar, R., 2006, September.Design of High-Speed-Pipelined Execution
Unit of 32-bit RISC Processor. In 2006 Annual IEEE India Conference (pp. 1-5). IEEE.
6. S. P. 6. Ritpurkar, M. N. Thakare and G. D. Korde, "Design and simulation of 32-Bit RISC architecture based on MIPS using
VHDL," 2015 International Conference on Advanced Computing and Communication Systems, 2015.Interaction, Optimization and
Robotic Applications (HORA) (pp. 1-6). IEEE.
7. Al-sudany, S.M., Al-Araji, A.S. and Saeed, B.M., 2021. FPGA-Based Multi-Core MIPS Processor Design. IRAQI JOURNAL OF
COMPUTERS, COMMUNICATION, CONTROL & SYSTEMS ENGINEERING, 21(2).
8. Wang, W., Han, J., Cheng, X. and Zeng, X., 2021. An energy-efficient cryptoextension design for RISC-V. Microelectronics
Journal, 115, p.105165.

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