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DATA FLOW and SEQUENCING
GRAPH
(Synthesis and Optimization of Digital Circuits)
Submitted to Submitted by
Mrs. Nivedita Shruti Shreya
Apoorva
Data Flow Graph
 Graphical representation of the "flow" of data through an
information system.
Represents a data dependencies between a number of
operations.
A data-flow graph G(V, E) is a directed graph whose vertex set V = {vi;
i = 1,2, . . . , n,) is in one-to-one correspondence with the set of tasks.
 Assumes that the values are preserved during their lifetime,
i.e., that some sort of storage (registers in case of synchronous
implementations) is provided.
Example
Consider the following model fragment describing a set
of computations
XI = x + dx:
ul = u-(3*x*u*dx)-(3*y*dx):
yl = y+u*dx;
c = xi < a;
Four assignments → a set of 11 simple operations
11 vertices are labeled by numeric identifiers
Input = {x, y, u, dx, a, 3)
Output = {XI, yl, ul, c}
Dfg &amp; sg ppt (1)
Reasons for existence of Data Flow Graph
Increasing demand for higher computation speed
Ability to specify algorithms
For this reason Data Flow Graphs have been used
successfully in the simulation of hardware like
computer systems.
Advantages of Data Flow Graphs
Compactness and general amenability to direct
interpretation.
The algorithms are controlled by the arrival of data at
the nodes.
Dfg &amp; sg ppt (1)
 A hierarchical control/data flow graph
 Control flow primitives modelled through hierarchy
 Data-flow & serialization dependencies modelled by
graphs
 Supports a model call
 Hierarchy of directed graphs represented by Gs(V,E)
 Generic element in the
hierarchy
 An extended data flow graph
having 2 kinds of vertices
 Operations
 Links
Example of a Sequencing
Graph
 2 submodels
 Submodel(a,z){x=a*b; y=x*c;
z=a+b}
 Submodel(m,n){p=m+n;
q=m*n}
 Vertex a,4
 Models the call to submodel
 Links the two graph entities
Example of a Hierarchical
Sequencing Graph
 Some vertices are links to other sequencing graph
entities representing
 Model call
 Branching
 Iteration Constructs
 Model call Vertex is a pointer to another sequencing
graph entity at a lower level in the hierarchy
 Can be modelled by
 Branching Clause
 Branching Bodies
 Set of tasks selected according to the value of branching
clause
 Execution is mutually exclusive
 Branching is modelled by associating a sequencing
graph entity with each branching body and a link
vertex with the branching clause
 Code sequence :
x=a*b; y=x*c; z=a+b;
if (z≥0) {p=m+n; q=m*n}
 Branching clause z≥0 is
calculated at a,4
 TRUE: Required operations
take place
 FALSE: No-operations Example of a Hierarchical Sequencing
Graph with a Branching Construct
 Are modelled by
 Iteration Clause
 Iteration Body/Loop
 A set of tasks repeated as long as the
iteration clause is true
 The adjacent circuit performs 3
tasks:
 Reading input data
 Iterating the evaluation of a set of
statements
 Writing the result to a port
 Vertex labeled LOOP evaluates
the iteration clause c
Example of a Hierarchical
Sequencing Graph with an Iteration
Construct
 Marking denotes the state of the corresponding
operation which can be
 Waiting for execution
 Executing
 Having completed execution
 Firing an operation means starting its execution
 Semantics of the model : an operation can be fired as
soon as all of its direct predecessors have completed
execution
 Attributes such as area or delay cost can be
attributed to the vertices and edges of a
sequencing graph model
 Delay can be
 Data dependent
 Data independent
 Operations with such delay are
 Data-dependent delay branching
 Data-dependent delay iteration
 Can be of two types
 Bounded
 Unbounded
 Can be estimated before synthesis
 Can be characterised by its overall delay called Latency
 Graphs with bounded delays are called bounded-latency
graphs
 Else they are called unbounded-latency graphs
 Used to model circuit behaviour at architectural level
 Can be cast as directed bipartite graphs
 Vertices correspond to
 Places (States)
 Transitions (Operations)
 Petri net model is more general and powerful
 Sets framework to state properties of general
concurrent circuits
Any Questions ???

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Dfg &amp; sg ppt (1)

  • 1. DATA FLOW and SEQUENCING GRAPH (Synthesis and Optimization of Digital Circuits) Submitted to Submitted by Mrs. Nivedita Shruti Shreya Apoorva
  • 2. Data Flow Graph  Graphical representation of the "flow" of data through an information system. Represents a data dependencies between a number of operations. A data-flow graph G(V, E) is a directed graph whose vertex set V = {vi; i = 1,2, . . . , n,) is in one-to-one correspondence with the set of tasks.  Assumes that the values are preserved during their lifetime, i.e., that some sort of storage (registers in case of synchronous implementations) is provided.
  • 3. Example Consider the following model fragment describing a set of computations XI = x + dx: ul = u-(3*x*u*dx)-(3*y*dx): yl = y+u*dx; c = xi < a; Four assignments → a set of 11 simple operations 11 vertices are labeled by numeric identifiers Input = {x, y, u, dx, a, 3) Output = {XI, yl, ul, c}
  • 5. Reasons for existence of Data Flow Graph Increasing demand for higher computation speed Ability to specify algorithms For this reason Data Flow Graphs have been used successfully in the simulation of hardware like computer systems. Advantages of Data Flow Graphs Compactness and general amenability to direct interpretation. The algorithms are controlled by the arrival of data at the nodes.
  • 7.  A hierarchical control/data flow graph  Control flow primitives modelled through hierarchy  Data-flow & serialization dependencies modelled by graphs  Supports a model call  Hierarchy of directed graphs represented by Gs(V,E)
  • 8.  Generic element in the hierarchy  An extended data flow graph having 2 kinds of vertices  Operations  Links Example of a Sequencing Graph
  • 9.  2 submodels  Submodel(a,z){x=a*b; y=x*c; z=a+b}  Submodel(m,n){p=m+n; q=m*n}  Vertex a,4  Models the call to submodel  Links the two graph entities Example of a Hierarchical Sequencing Graph
  • 10.  Some vertices are links to other sequencing graph entities representing  Model call  Branching  Iteration Constructs  Model call Vertex is a pointer to another sequencing graph entity at a lower level in the hierarchy
  • 11.  Can be modelled by  Branching Clause  Branching Bodies  Set of tasks selected according to the value of branching clause  Execution is mutually exclusive  Branching is modelled by associating a sequencing graph entity with each branching body and a link vertex with the branching clause
  • 12.  Code sequence : x=a*b; y=x*c; z=a+b; if (z≥0) {p=m+n; q=m*n}  Branching clause z≥0 is calculated at a,4  TRUE: Required operations take place  FALSE: No-operations Example of a Hierarchical Sequencing Graph with a Branching Construct
  • 13.  Are modelled by  Iteration Clause  Iteration Body/Loop  A set of tasks repeated as long as the iteration clause is true  The adjacent circuit performs 3 tasks:  Reading input data  Iterating the evaluation of a set of statements  Writing the result to a port  Vertex labeled LOOP evaluates the iteration clause c Example of a Hierarchical Sequencing Graph with an Iteration Construct
  • 14.  Marking denotes the state of the corresponding operation which can be  Waiting for execution  Executing  Having completed execution  Firing an operation means starting its execution  Semantics of the model : an operation can be fired as soon as all of its direct predecessors have completed execution
  • 15.  Attributes such as area or delay cost can be attributed to the vertices and edges of a sequencing graph model  Delay can be  Data dependent  Data independent
  • 16.  Operations with such delay are  Data-dependent delay branching  Data-dependent delay iteration  Can be of two types  Bounded  Unbounded
  • 17.  Can be estimated before synthesis  Can be characterised by its overall delay called Latency  Graphs with bounded delays are called bounded-latency graphs  Else they are called unbounded-latency graphs
  • 18.  Used to model circuit behaviour at architectural level  Can be cast as directed bipartite graphs  Vertices correspond to  Places (States)  Transitions (Operations)  Petri net model is more general and powerful  Sets framework to state properties of general concurrent circuits