Dynamic logic circuits
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This document discusses dynamic logic circuits. It notes that dynamic logic circuits offer advantages over static logic circuits by temporarily storing charge in parasitic capacitances rather than relying on steady-state behavior. Dynamic logic circuits require periodic clock signals to control charge refreshing and allow for simple sequential circuits with memory. They can implement logic in smaller areas and thus consume less power than static logic. The document then discusses several examples of dynamic logic circuits like dynamic CMOS TG logic, domino CMOS logic, NORA logic, and their operating principles. It also covers issues like charge leakage and charge sharing that need to be addressed in dynamic logic circuits.
Dynamic logic circuits
- 1. Kalyan Kumar Kalita M.Tech(ECE) Roll No:- 1403206003 GIMT Azara E-mail: [email protected] 10/30/2014 1
- 2. Dynamic Logic Dynamic logic circuits offer several significant advantages over static logic circuits. The operation of all dynamic logic gates depends on temporary storage of charge in parasitic node capacitances, instead of relying on steady-state circuit behavior. 10/30/2014 2
- 3. Dynamic logic circuits require periodic clock signals in order to control charge refreshing. The capability of temporary storing a state, at a capacitive node allows us to implement very simple sequential circuits with memory functions. Common clock signals synchronize the operation of various circuit blocks. 10/30/2014 3
- 4. Power consumption increases with the parasitic capacitances. Therefore dynamic circuit implementation in smaller area, consumes less power than the static logic. 10/30/2014 4
- 5. Dynamic CMOS TG Logic 10/30/2014 5
- 6. TG Dynamic Shift Register 10/30/2014 6
- 7. Single Phase TG Shift Register 10/30/2014 7
- 9. Domino CMOS Logic 10/30/2014 9
- 10. Domino CMOS Logic 10/30/2014 10
- 11. Cascading Domino CMOS Logic 10/30/2014 11
- 12. NORA Logic 10/30/2014 12
- 13. When the clk signal is low, the output nodes of nMOS logic blocks are pre-charged to VDD through the pMOS pre-charge transistors, whereas the output nodes of pMOS logic blocks are pre-discharged to 0V through the nMOS discharge transistors driven by ø. 10/30/2014 13
- 14. When the clock signal makes a low to high transition, where as the inverted signal makes a high-to-low transition simultaneously, all cascaded nMOS and pMOS logic states evaluate one after the other, much like the domino CMOS Logic. The advantage of NORA CMOS logic is that a static CMOS inverter is not required at the output of every dynamic logic stage. 10/30/2014 14
- 15. NORA CMOS Logic Circuit 10/30/2014 15
- 16. NORA CMOS Logic Circuit 10/30/2014 16
- 17. Zipper CMOS Logic Circuit 10/30/2014 17
- 18. TSPC Dynamic CMOS 10/30/2014 18
- 19. Charge Leakage The operation of a dynamic gate relies on the dynamic storage of the output value on a capacitor. If the pull-down network is off, the output should remain at the precharged state of VDD during the evaluation stage. This current gradually leaks away due to leakage currents. Source 1 and 2 are the reversed-biased diode and subthreshold leakage of the NMOS pull-down device M1, respectively. The charge stored on CL will slowly leak away through these leakage channels. 10/30/2014 19
- 20. Dynamic circuit therefore require a minimal clock rate, which is typically on the order of a few kHz. Note that the PMOS precharge device also contributes some leakage current due to the reverse bias diode and the subthreshold conduction. Leakage is caused by the high-impedance state of the output node during the evaluate mode, when the pull-down path is turned off. The leakage problem may be counteracted by reducing the output impedance on the output node during evaluation. This is often done by adding a bleeder transistor. The only function of the bleeder –an NMOS style pull-up device. 10/30/2014 20
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- 22. Charge Sharing 10/30/2014 22
- 23. Another important concern in dynamic logic is the impact of change sharing. During the precharge phase, the output node is precharged to VDD. Assume that all inputs are set to 0 during precharge, and that the capacitance Ca is discharged. Assume further that input B remains at 0 during evaluation, while input A makes a 0-1 transition, turning transistor Ma on. The change stored originally on capacitor CL is redistributed over CL and Ca. This causes a drop in the output voltage, which cannot be recovered due to the dynamic nature of the circuit. 10/30/2014 23
- 24. Thank U 10/30/2014 24