Embedded System Programming on ARM Cortex M3 and M4 Course

Editor's Notes

• #14: Programming and Debugging using Keil Debugging using Logic analyzers And many ….
• #22: First Processor start with thread mode and privileged access level Changing CONTROL[0]=1 move the processor into un-privileged mode Its not possible to come back to priv level at this stage Issue a processor exception Processor executes exception handler in handler mode with privileged access level making CONTROL[0]=0 makes return to privileged level Otherwise processor return to un-privileged level
• #28: This is used to hold the return address when calling a function or subroutine. When a function call or subroutine call is made the value of LR Is updated automatically with the address of the instruction where it needs to return . LR also used to trigger a return from exception handling
• #33: The APSR contains the Status flags of integer operations (N-Z-C-V bits) resulted from previous instruction exaction
• #35: The IPSR contains the exception type number of the currently executing handler
• #36: used to mask/unmask exceptions globally They can only be accessed in the privileged access
• #37: The selection of stack pointer (MSP/PSP) nPRIV bit indicates in which level the processor currently executing. The CONTROL register can only be accessed in the privileged access level
• #40: CMSIS
• #54: A 512 MB memory space primarily for program code, including the default vector table
• #56: The peripheral memory region also has the size of 512MB, used mostly for on-chip peripherals. Similar to SRAM region, the first 1MB of the peripheral region is bit addressable if the optional bit-band feature is included. You can not execute instruction code from here
• #65:  Aligned Transfer, means that the data's address value is a multiple of the data's type-size (in bytes). WORD size transfers are carried out to addresses that are a multiple of 4. i.e. 0x00000000, 0x00000004, 0x00000008, … Half Word size transfers are carried out to addresses that are a multiple of 2: 0x00000000, 0x00000002, 0x00000004, … SRAM Space Wasted
• #66: When an unaligned transfer is issued by the processor they are actually converted in to multiple aligned transfer by the processor bus interface unit. Since it is broken into several separate aligned transfers and as a result it takes more clock cycles for a single data access and might not be good in situations in which high performance is required . Effective utilization of SRAM space
• #68: Instruction will be fetched in a word boundary since all Thumb instructions are half-word aligned in memory, two Thumb instructions are fetched at a time. It it’s a 32 bit instruction then, single instruction will be fetched at a time.
• #72: Bit band Operations can only be operated on 2 memory regions. This is called bit-band region 0x20000000 to 0x20100000 (1 MB) 0x40000000 to 0x40100000(1 MB) To Set/Reset any bit field in the Bit band region , we have to use Bit band alias address in the Bit band alias region 0x22000000 to 0x23ffffff (31 MB) 0x42000000 to 0x43ffffff(31 MB)
• #73: 0x22000008 is called alias address for bit2 of the address 0x20000000
• #74: Each individual bit of the bit-band region can be accessed separately by using the least significant bit of each word-aligned bit band alias address Memory rampaging is performed during bus transfer No special instruction being used.
• #77: This can be used to simplify branch decisions. For example if a branch should be carried based on one single bit in a status register in a peripheral
• #78: Avoid race condition : When you want to change the value of a shared memory or register , using bit band operation is a good choice !!! Its atomic : when you are accessing the bit band region , by means of its bit band alias address , no interrupt can disturb it until it finishes.
• #91: The processor uses a full descending stack model When the processor pushes a new item onto the stack, it first decrements the stack pointer and then writes the item to the new memory location. This means the stack pointer holds the address of the last stacked item in memory
• #107: External interrupts : External means, external to the processor core. When we integrate the processor in micro controller , external interrupts are usually generated by the peripherals , like timers, GPIOs, serial protocols like SPI,I2C, etc.
• #120: The priority level register is divided into 2 parts pre-empt priority field (the upper half) Sub-priority field (the bottom half)
• #121: 8 bits which are shared among those fields is decided by the field “priority group” in the "application interrupt and Reset Control register"
• #123: so, when priority group is 0 (default) then we have 8 levels of pre-empt priority and no sub priority
• #124: That means for every pre empt level there are two levels of sub priority
• #126: CMSIS core Provides Various API's to Configure interrupt Priorities. Remember it is highly recommended to use CMSIS api's instead of hardcoding Registers directly, it makes your code Portable
• #130: You can enable any interrupt in 2 easy steps Set up the priority level of the required interrupt (optional) II. Enable the interrupt in the NVIC.
• #131: The PRIMASK register is used to disable all exceptions except NMI and hard fault
• #132: FAULTMASK is just like PRIMASK except that, it blocks even Hard-Fault exception (RESET, NMI cant be blocked)
• #133: In some cases, you might want to disable interrupts only with priority lower than a certain level. In this case, you could use the BASEPRI register.
• #135: Interrupt Request Caused pending bit to be Set
• #148: When the SysTick timer Exception handler is running, if you issue button interrupt it will pre-empt the sysTick handler SysTick Handler will run when the Button ISR has finished If the button ISR is running, when the SysTick Exception occurs, then it cant pre-empt the Button ISR.
• #150: SysTick Exception will be raised for every 125 micro seconds
• #152: When the SysTick timer exception handler is running, if you issue button interrupt it wont preempt the first one Button ISR will run when the Systick handler has finished If the button ISR is running, when the SysTick Exception occurs, then Button ISR Will be Pre-empted.
• #162: The NVIC_IABR0 to NVIC_IABR7 registers indicate which interrupts are active at given point in time. Each external interrupt has an active status bit. When the processor starts the interrupt handler, the bit is set to 1 automatically and cleared automatically when the interrupt return is executed These registers are Read Only.
• #163: The NVIC_IPR0 to NVIC_IPR59 registers provide an 8-bit priority field for each interrupt and each register support setting priority for 4 interrupts These registers are byte-accessible.
• #165: “welcome to the world of vector table “
• #167: On system reset, the vector table is fixed at address 0x00000000 at the code memory Privileged code can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80
• #169: The vector table relocation feature provides a programmable register called the Vector Table Offset Register(VTOR). This register defines the starting address of the memory being used as the vector table. The VTOR reset value zero.
• #170: After the reset always processor excepts vector table to be at 0x00000000 The boot code in the ROM code ,executes and does required setup Then the boot loader relocate the vector table to new vector table address in user flash and calls the reset handler of the new vector table Application in user flash now uses new vector table
• #186: As the
• #189: With a svc instruction application can ask the kernel to get services Different services may have different number which application pass with a SVC instruction
• #191: SVC makes application tasks to be developed independently of the OS Application tasks do not need to know the programming details of the underlying hardware . The application tasks only need to know the SVC service number and the parameters that the os services requires.
• #194: SVC_number = (uint8_t) *( (Next_ins_addr_after_svc ) – 2 ) +6 This gives the address Where svc insturction is stored in the code memory
• #199: The PendSV exception solves the problem by delaying the context switching request until all the IRQ handlers have completed their processing