embedded_in_Arduino_with_basic_embedded.pptx

Editor's Notes

• #7: Processor There are two classifications of computers: complex instruction set computer (CISC) and reduced instruction set computer (RISC). In reality, there is a spectrum of architectures that we can classify as CISC or RISC. We make these general observations when deciding whether to call a computer CISC or RISC: Complex instruction set computers (CISC) Early computers offered CPUs that were much faster than available memories. Fetching instructions limited performance A single complex instruction could perform many operations Example: Find the zeros of a polynomial Complex instructions require many processor clock cycles to complete and most instructions can access memory A program running on a CISC computer employed a relatively small number of complex instructions High code density, many instruction types w/ varying length, fewer and specialized registers, many addressing modes Complexity is embedded in the processor hardware (overhead) Examples: Intel (x86), Freescale 9S12 Reduced Instruction Set Computers (RISC) Memories match CPU speed No large penalty for instruction fetch Instructions simplified Example: dedicated load/store instructions, regular instructions can not access memory but only registers Single processor clock cycle per instruction (pipelined) A program running on a RISC computer employs a relatively larger number of simplified instructions Reduced code density, few instructions w/ fixed delay (pipeline!), many identical general-purpose registers, few addressing modes Complexity exists in the assembly code generated by the programmer or compiler, hardware is simple (low overhead/low power) Examples: LC3, MIPS, ARM, SPARC, PowerPC Which architecture is best is beyond the scope of this class, but it is important to recognize the terminology. It is very difficult to compare the execution speed of two computers, especially between a CISC and a RISC. One way to compare is to run a benchmark program on both, and measure the time it takes to execute. Time to execute benchmark = Instructions/program * Average cycles/instruction * Seconds/cycle For example, the 50 MHz ARM Cortex M has one bus cycle every 20ns. One average it may require 1.5 cycles per instruction. If the benchmark program executes 10,000,000 assembly instructions, then the time to execute the benchmark will be 0.3 seconds. Memory: EPROMs are Erasable Programmable ROMs. The mechanism used to erase and write is UV light EEPROMs are Electrically Erasable Flash memory is like EEPROM however writes are performed in large blocks as opposed to single bytes. Cheaper hence popular DRAMs require a periodic refresh SRAMs don’t. Both are volatile therefore are lost when powered down. Interfaces: Parallel - binary data is available simultaneously on groups of lines Serial - binary data is available one bit at a time on a single line Analog - data is encoded as a variable voltage Time - data is encoded as a period, frequency, pulse width or phase shift I/O Memory-mapped I/O I/O ports/registers appear as addresses on common bus with memory I/O ports/registers are accessed as though they are locations in memory Employed on the ARM, Freescale and TI processors I/O-mapped I/O I/O ports/registers have separate control signals from those used with memory Special instructions are used to access I/O ports/registers Employed on Intel x86 processors
• #8: Requirements are broad and Specifications go into the details.
• #36: Be sure to point out the what all of the buttons do.
• #37: All connections to computers- mice, printers etc use a serial port. Gotta pick the right one.
• #38: All connections to computers- mice, printers etc use a serial port. Gotta pick the right one.