Field programable gate array
27 likes4,701 views
An FPGA is a programmable logic device containing an array of configurable logic blocks and interconnects that can be programmed to perform different logic functions. It allows reprogramming to perform different functions in microseconds. The key parts of an FPGA are I/O blocks around the edge to interface with other components, logic blocks in the interior to implement logic functions, and interconnects to connect the blocks. FPGAs are programmed by configuring electronic switches to define logic functions and connect the blocks as required.
Field programable gate array
- 1. FIELD PROGRAMABLE GATE ARRAYPREPARED BY:- NEHA AGARWAL B.TECH(EC) Vth SEM BTBTE08057
- 2. WHAT IS FPGA?a PLD with high density and capable of implementing different functions in a short period of time
- 3. silicon chip containing an array of configurable logic blocks (CLB)
- 4. can be reprogrammed to perform a different function in a matter of microsecondsWHAT IS FPGA?
- 5. WHAT IS PROGRAMMABLE LOGIC DEVICE (PLD)?is an electronic component used to build reconfigurable digital circuits
- 6. has an undefined function at the time of manufacture
- 7. before using in a circuit it must be programmed or reconfigured
- 8. can be customized as per needs of the user by programming
- 9. can be reprogrammed in case of problemsARCHITECTURE OF FPGAThere are three key parts of a FPGA structure: I/O BLOCKS: it forms a ring around the outer edge of the structureINTERCONNECTS: connects logic blocks to logic blocks and I/O blocks to logic blocksLOGIC BLOCKS: Inside the ring of I/O blocks lies a rectangular array of logic blocks.
- 11. ARCHITECTURE OF FPGA:I/O BLOCKSFPGAs provide support for I/O standards providing interface bridge in a system.
- 12. I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards.ARCHITECTURE OF FPGA:LOGIC BLOCKSThe logic blocks in an FPGA are generally nothing more than a couple of logic gates or a look-up table and a flip-flop.
- 13. Its purpose is to implement combinational and sequential logic functions.
- 14. Logic blocks can be implemented by:-Transistor pairsMultiplexers Look up tables( LUT)Wide fan-in AND-OR structure.
- 15. ARCHITECTURE OF FPGA: ROUTING MATRIXAn FPGA device contains flexible programmable routing matrix which is used to connect logic blocks with each other.
- 16. There are various type of connection lines in FPGA:long lines are used to connect distant logic blocksshort lines connect neighboring blocks with each otherdedicated clock trees are used to distribute synchronization signalsdedicated set/reset lines are used to reset all flip-flops in the FPGA
- 17. HOW FPGA WORKS?
- 18. HOW FPGA WORKS?When a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segmentsPROGRAMMING A FPGAUnderstand and define design requirements
- 21. Synthesis
- 22. Implementation
- 23. Translate
- 24. Mapping
- 25. Place and Route
- 26. Timing or Post layout simulation
- 27. Programming, Test and DebugPROGRAMMING A FPGAThis is how a program in any HDL is loaded on the FPGA or any other PLD.PROGRAMMING METHODOLOGYElectrically programmable switches are used to program FPGA
- 28. Properties of programmable switch determine: resistance, volatility, reprogrammability, size etc.
- 29. Various programming techniques are:SRAM PROGRAMMING TECHNOLOGY EPROM/EEPROM PROGRAMMING TECHNOLOGYANTIFUSE PROGRAMMING METHODOLOGY
- 30. PROGRAMMING METHODOLOGY: SRAM PROGRAMMING TECHNOLOGYUse Static RAM cells to control pass gates or multiplexers
- 31. SRAM cells control the configuration of logic block as well
- 32. Advantage:Fast re-programmability, lesser configuration timeIn-circuit re-programmableDisadvantage:SRAM is volatile Requires large areaNeeds an external storageNeeds a power-on configuration mechanism
- 33. PROGRAMMING METHODOLOGY: EPROM/EEPROM PROGRAMMINGTech used in EPROM and EEPROM devices is used Switch is disable by applying high voltage to gate-2 between gate-1 and drain.
- 34. The charge is removed by UV light
- 35. AdvantageNo external permanent memory is needed to program it at power-upRe-programmable by exposing to UV radiation or high voltageDisadvantageConsumes static powerNot in-system re-programmable
- 36. PROGRAMMING METHODOLOGY: ANTIFUSE PROGRAMMING METHODOLOGYtwo terminal device with an un-programmed state present very high resistance
- 37. By applying high voltage create a low resistance link
- 38. AdvantageSmall sizeRetain configuration after power offDisadvantageOne Time Programmable
- 39. ADVANTAGE DISADVANTAGEfaster response times
- 40. reduced time to market
- 41. low cost
- 43. reduced development time and risk
- 45. FPGAs are generally slower than application-specific integrated circuit (ASIC)
- 46. It cannot handle complex designs
- 47. draw more powerAPPLICATIONSaerospace & defense
- 48. automotive
- 49. broadcast
- 51. fulfilling industrial/ scientific/ medical needs
- 53. wired communicationsREFERENCEWEB REFERENCE:http://www.cse.iitb.ac.in/~cs330/FPGA-Arch.pptwww.fpgacentral.com http://en.wikipedia.org/wiki/Field_Programmable_Gate_ArrayBOOK REFERNECE:FPGA ARCHITECTURE Survey and Challenges by Ian Kuon (University of Toronto, Canada), Russell Tessier (University of Massachusetts, Amherst, USA) & Jonathan Rose (University of Toronto, Canada)
- 54. THANK YOU