Gq3511781181

Amit Jain et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1178-1181

RESEARCH ARTICLE

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OPEN ACCESS

FPGA Based Implementation for Ripple Carry Adder with
Reduced Area and Low Power Consumption
Amit Jain, Nitin Meena
IES College of Technology Bhopal, M.P.

Abstract
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters,
digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and
are trying to design multipliers which offer either of the following- high speed, low power consumption,
regularity of layout and hence less area or even combination of them in multiplier. However area and speed are
two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best
trade off solution among the both of them.
While comparing the adders we found out that Ripple Carry Adder had a smaller area while having lesser speed,
in contrast to which Carry Select Adders are high speed but possess a larger area. And a Carry Look Ahead
Adder is in between the spectrum having a proper tradeoff between time and area complexities.
Keywords: -Ripple Carry Adder, Carry Select Adder, Carry Skip Adder, Carry Look Head Adder FIR Filter.
I.
INTRODUCTION
Addition usually impacts widely the overall
performance of digital systems and a crucial arithmetic
function. In electronic applications adders are most
widely used. Applications where these are used are
multipliers, DSP to execute various algorithms like
FFT, FIR and IIR. Wherever concept of multiplication
comes adders come in to the picture. As we know
millions of instructions per second are performed in
microprocessors. So, speed of operation is the most
important constraint to be considered while designing
multipliers.
Improved
adders
generate
carries o
simultaneously [1]. These adders employ the principle
that the carry from each bit position may be generated
independently as an explicit function of all the less
significant addend and augend bits. However, because
of the inherent limitations in available components, the
constructors of simultaneous carry- generation adders
are not always practical.
Multiplication is a fundamental operation in
most signal processing algorithms. Multipliers have
large area, long latency and consume considerable
power. Therefore low-power multiplier design has
been an important part in low- power VLSI system
design. There has been extensive work on low-power
multipliers at technology, physical, circuit and logic
levels. A system’s performance is generally
determined by the performance of the multiplier
because the multiplier is generally the slowest element
in the system. Furthermore, it is generally the most
area consuming. Hence, optimizing the speed and area
of the multiplier is a major design issue. However,
area and speed are usually conflicting constraints so
that improving speed results mostly in larger areas. As
a result, a whole spectrum of multipliers with different
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area- speed constraints has been designed with fully
parallel.
The rest of the paper is organized as follows.
In section 2, a brief about ripple carry adder, carry
select adder and carry skip is given. In section 3 carry
look head adder is introduced along with partitioning
methodology. Also a new architecture with clock
sharing is introduced. Section 4 provides the
simulation results obtained. Section 5 provides the
conclusion and future scope obtained.
II.
ADDITION ALGORITHM
Ripple Carry Adder
This procedure is an asynchronous addition
used in the first electronic computers. Addition of
binary numbers of several digits is accomplished in
the same manner as that of decimal numbers.
Concatenating the N full adders forms N bit Ripple
carry adder. In this carry out of previous full adder
becomes the input carry for the next full adder. It
calculates sum and carry according to the following
equations. As carry ripples from one full adder to the
other, it traverses longest critical path and exhibits
worst case delay.
S i  Ai  Bi  Ci
(1)

Ci 1  Ai  Bi  Bi  Ci  Ci  Ai

(2)

Where i = 0, 1, 2, 3 …n-1
RCA is the slowest in all adders but it is very
compact in size. If the ripple carry adder is
implemented by concatenating N full adders, the delay
of such an adder is 2N gate delays from Cin to Cout.
The delay of adder increases linearly with increase in
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number of bits. Block diagram of RCA is shown in
Figure 1.

within the group are pi=1, carry bypasses the entire
group as shown in figure 2.

X3

Y2 X2
C3

FA

Y1 X1
C2

FA

S3

FA

S2

4-bit
block

Y0 X0
C1

S1

0

,

c

carry-in (

0
i

, ;

c

k

1

s

i 1:k

,

1

c ) , later as the block’s true
i

) becomes known , the correct signal

pairs are selected. Generally multiplexers are used to
propagate carries.
an-1 bn-1.. an/2 bn/2

N/2-bit
RCA

an/2-1 bn/2-1 .. a0 b0

N/2-bit
RCA

1

N/2-bit
RCA

0

1
MUX

0

ci=0
Low Sn/2

High Sn/2
Figure 2: A Carry Select Adder with 1 level using n/2bit RCA

Because of multiplexers larger area is
required.
Have a lesser delay than Ripple Carry Adders (half
delay of RCA).
Hence we always go for Carry Select Adder while
working with smaller no of bits.
o

Carry Skip Adder
A carry skip divides the words to be added in
to groups of equal size of k-bits. Carry Propagate pi
signals may be used within a group of bits to
accelerate the carry propagation. If all the pi signals
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Skip

3210

O
R

Figure 3: Carry Skip Adder

Carry Select Adder
In Carry select adder scheme, blocks of bits
are added in two ways: one assuming a carry-in of 0
and the other with a carry-in of 1.This results in two
precomputed sum and carry-out signal pairs
i 1:k

Skip

S0

o

s

4-bit
block

C0

FA

Figure 1: Block Diagram of RCA

(

4-bit
block

Skip

Y3
C4

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In this way delay is reduced as compared to
ripple carry adder. The worst-case carry propagation
delay in a N-bit carry skip adder with fixed block
width b, assuming that one stage of ripple has the
same delay as one skip, can be derived:
Block width tremendously affects the latency
of adder. Latency is directly proportional to block
width. More number of blocks means block width is
less, hence more delay. The idea behind Variable
Block Adder (VBA) is to minimize the critical path
delay in the carry chain of a carry skip adder, while
allowing the groups to take different sizes. In case of
carry skip adder, such condition will result in more
number of skips between stages.
Such adder design is called variable block design,
which is tremendously used to fasten the speed of
adder. In the variable block carry skip adder design we
divided a 32-bit adder in to 4 blocks or groups. The bit
widths of groups are taken as; First block is of 4 bits,
second is of 6 bits, third is 18 bit wide and the last
group consist of most significant 4 bits.
o

Ripple Carry Adder
In ripple carry adders, the carry propagation
time is the major speed limiting factor as seen in the
previous lesson.
Most other arithmetic operations, e.g. multiplication
and division are implemented using several
add/subtract steps. Thus, improving the speed of
addition will improve the speed of all other arithmetic
operations.
Accordingly, reducing the carry propagation
delay of adders is of great importance. Different logic
design approaches have been employed to overcome
the carry propagation problem.
One widely used approach employs the principle of
carry look-ahead solves this problem by calculating
the carry signals in advance, based on the input
signals.
This type of adder circuit is called as carry look-ahead
adder (CLA adder). It is based on the fact that a carry
signal will be enerated in two cases:
(1) when both bits Ai and Bi are 1, or
(2) when one of the two bits is 1 and the carry-in
(carry of the previous stage) is 1.

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To understand the carry propagation problem, let’s
consider the case of adding two n-bit numbers A and
B.

and equations. Computed values of all the Gi’s are
valid one AND-gate delay after the operands A and B
are made valid.

In this circuit, the 2 internal signals P i and Gi are given
by:
Pi  Ai  Bi
(3)

III.
RESULT AND SIMULATION
We have implemented Ripple Carry Adder
(RCA), Carry Select Adder (CSA), and Carry Lookhead Adder (CLA architecture. A comparison between
RCA, CSA and CLA design based architecture for 4bit, 16-bit is given in Table I and Table II respectively.

Gi  Ai  Bi

(4)

The output sum and carry can be defined as:

S i  Pi  C i
C0

(5)

Ci 1  Gi  Pi Ci

(6)

A0

S0

C0
P0- - - - - - - - P0

B0
G0
S1
P1- - - - - - - - P1
G1
C2

S2

P2- - - - - - - - P2
G2
C3

S3

P2- - - - - - - - P2
G3

Figure 4: Carry Look head Block
Gi is known as the carry Generate signal since
a carry (Ci+1) is generated whenever Gi =1, regardless
of the input carry (Ci).
Pi is known as the carry propagate signal since
whenever Pi =1, the input carry is propagated to the
output carry, i.e., Ci+1. = Ci (note that whenever Pi =1,
Gi =0).
Thus, these signals settle to their steady-state
value after the propagation through their respective
gates.
Computed values of all the Pi’s are valid one XORgate delay after the operands A and B are made valid.
Computing the values of Pi and Gi only depend on the
input operand bits (Ai & Bi) as clear from the Figure
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TABLE I
Comparison between RCA, CSA and CLA design
based architecture for 4-bit
RCA
CSA
CLA
Number
of 4 out of
7 out of 6 out of
Slices
6144
6144
6144
Number of 4 8 out of
13 out 10 out of
input LUTs
12288
of
12288
12288
Maximum
7.087ns
6.431ns 7.435ns
combinational
path delay
TABLE II
Comparison between RCA, CSA and CLA design
based architecture for 16-bit
RCA
CSA
CLA
Number
of 18 out of 28 out 20 out of
Slices
6144
of
6144
6144
Number of 4 32 out of 52 out 35 out of
input LUTs
12288
of
12288
12288
Maximum
14.431ns 10.338ns 14.652ns
combinational
path delay
Implementing the proposed CLA based architecture
has been captured by VHDL and the functionality is
verified by RTL and gate level simulation. To estimate
the number of slices, flip flop, required time and
minimum period information for ASIC design, we
have used Xilinx Design Compiler to synthesize the
design into gate level. Comparison of practical result
up to third decomposition level architecture for 2-D
DWT is given in Table I and Table II respectively.
IV.
CONCLUSION
We studied about different adders among
compared them by different criteria like number of
slice and Time so that we can judge to know which
adder was best suited for situation. After comparing all
we came to a conclusion that Carry Look-head
Adders are best suited for situations where Speed is
the only criteria. Similarly Ripple Carry Adders are
best suited for Low Power Applications. But Among
all the Carry Look Ahead Adder had the least AreaDelay product that tells us that, it is suitable for
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situations where both low power and fastness are a
criteria such that we need a proper balance between
both as is the case with our Paper.

REFERENCES
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[2]

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[9]

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