IMPLEMENTATION OF 128-BIT SPARSE KOGGE-STONE ADDER USING VERILOG
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The document discusses the implementation of a 128-bit sparse Kogge-Stone adder in Verilog, highlighting its advantages over classical adders in terms of speed and efficiency due to its parallel processing capabilities. It emphasizes the Kogge-Stone adder's minimal fan-out and logic depth, making it the fastest among existing adder designs. Simulation results indicate that the sparse Kogge-Stone adder outperforms other adders in terms of delay and resource utilization, especially in portable device applications.
![International Journal of Technical Research and Applications e-ISSN: 2320-8163,
www.ijtra.com Volume 2, Issue 4 (July-Aug 2014), PP. 90-92
90 | P a g e
IMPLEMENTATION OF 128-BIT SPARSE
KOGGE-STONE ADDER USING VERILOG
Geeta Rani1, Sachin Kumar2
1
M.Tech Student, 2
Faculty
Department of Electronics & Communication M. Tech Student
MERI COLLEGE OF ENGINEERING & TECHNOLOGY
Sampla
Abstract— Parallel Prefix adders have been one of the most
notable among several designs proposed in the past. The
advantage of utilizing the flexibility in implementing these
structures based upon through put requirements. Due to
continuing integrating intensity and the growing needs of
portable devices, low power and high performance designs are of
prime importance. The classical parallel prefix adder structures
presented in the literature over the years optimize for logic depth,
area, and fan-out and interconnect count of logic circuits. In this
proposed system, Kogge-Stone adder which is one of types of
parallel prefix adder is used. Kogge stone is the fastest adder
because of its minimum fan-out. When parallel prefix adder is
compared with classical adders it is advantageous in every aspect.
The study reveals that Parallel Prefix adder has the least power
delay product when compared with its peer existing adder
structures (Ripple carry adder, Carry save adders etc).
Simulation results are verified using Xilinx 10.1 and
MODELSIM 6.4a softwares.
Key words— Carry Tree Adder, Kogge-Stone Adder, Sparse
Kogge-Stone Adder.
I.INTRODUCTION
Arithmatic operations i.e. addition, multiplication are
common in digital circuits. Binary adders are most basic and
widely used arithmetic operations and play a vital role in
determining the performance of a design. The basic need from
the circuit is that it has less computational time and is of small
size.
Adders when we talk about adders what we think most
probably person will think that it is a device that can add two or
more numbers. It is perfectly correct definition. However we
just discuss here about digital adders. Adder is a digital circuit
that uses in computers and in processors as in there arithmetic
and logic unit as well in other parts of processor that use to
calculate addresses table indices and other similar operations.
Most common adders operate on binary numbers. Basically
adders are of two types: Half adder and Full adder. Two half
adders can construct one full adder and full adder further
construct many complex adders such as ripple carry adder,
carry look-ahead adder and carry select adder etc. Basic adders
were the slow one. Generally Ripple carry adder (parallel
adder) was used to carry out binary addition. Many researches
done over several years to find a suitable technique for parallel
adders so that delay [1] can be minimized, performance can be
better. Hence to reduce the computation time, engineers
proposed faster ways by using Carry Look-Ahead (CLA)
adder. It uses the parallel prefix operation. In this paper, one of
parallel prefix adder is discussed.
II.CARRY-TREE ADDER
Carry tree adder is also known as the Parallel-Prefix
adder. In tree adders, carries are [2] generated in parallel and
fast computation is obtained at the expense of increased area
and power. The main advantage of the design is that the carry
tree [6] reduces the number of logic levels (N) by essentially
generating the carries in parallel.
III.EXISTING PARALLEL PREFIX ADDERS
The prominent parallel prefix tree adders, that are invented
so far are, Kogge-Stone, Brent-Kung, Han-Carlson, and
Sklansky. There exists various architectures fro carry
calculation part. Tradeoff in these architecture involves:
Area of adder
Its depth
The fan-out of the nodes
The overall wiring network.
Out of these, it was found from the literature that Kogge-
stone adder is the fastest adder when compared to other adders.
Kogge-Stone adder implementation [7] is most straightforward,
and also it has one of the shortest critical paths of all tree
adders. The drawback with the Kogge-Stone adder
implementation is the large area consumed and the more
complex routing (Fan-Out) of interconnects. The two signals
that are generated during various stages:
Propagate: controls whether a carry is propagated from
lower bits to higher bits.
Generate: controls whether a carry is generated.
Figure 1: Three stage structure for carry tree adder
Fig.1 is the three stage structure for carry tree adder. As
there are three stages in parallel [5] prefix adder, below is the
description of stages:
1. Pre-processing: Generate(Pi, Gi) from Ai, Bi)
Pi = Ai ⨁ Bi ………(1)
Gi = Ai . Bi ………(2)
2. Carry look-Ahead network: Generate (Pij, Gij) from
(Gi, Pi) and (Gj, Pj) [5]
Pi:j = Pi:k+1 . Pk:j …………(3)
Gi:j = Gi:k+1 | (pi:k+1 . Gk …………(4)](https://image.slidesharecdn.com/ijtra1407116-151026143154-lva1-app6892/85/IMPLEMENTATION-OF-128-BIT-SPARSE-KOGGE-STONE-ADDER-USING-VERILOG-1-320.jpg)
![International Journal of Technical Research and Applications e-ISSN: 2320-8163,
www.ijtra.com Volume 2, Issue 4 (July-Aug 2014), PP. 90-92
91 | P a g e
3. Post processing:
Sumi = Pi ⨁ Carryi-1 ………(5)
Ci = Gi:0 or (Cin and pi:0) ………(6)
IV.KOGGE-STONE ADDER
The Kogge-Stone adder concept [3] was developed by Peter
M. Kogge and Harold S. Stone, which they published in 1973
in a seminal paper titled “A Parallel Algorithm for the Efficient
Solution of a General Class of Recurrence Equations”. First the
focus is on the Kogge-Stone adder has minimal logic depth and
fan-out. The number of stages are log N, fan-out 2 at each stage
and have long wires. Fig. 2 & 3 are the Black cell and grey
cells description.
Figure 2(a): Schematic of Black cell
Figure 2(b): Symbol of Black cell
Figure 3(a): Schematic of Grey cell
Figure 3(b): Symbol of Grey cell
Kogge-stone adder design:
Step 1: First to generate propagation and generation signals
for each bit. [9]
Step 2: to generate black cell and grey cell equations.
Step 3: in each step grey cell generated.
Step 4: By using grey cell equation to generate the carry
bits directly.
Step 5: To combine Propagation and carry bits for each step
to generate sum.
Fig. 4 gives the 16-Bit Kogge-Stone adder.
Figure 4: 16-bit Kogge-Stone Adder
V.SPARSE KOGGE-STONE ADDER
Enhancements to the original implementation include
increasing the radix and sparsity of the adder. The radix of the
adder refers to how many results from previous level of
computation are used to generate the next one. Doing so
increases the power and delay of each stage, but reduces the
number of required stages. The sparsity of the adder refers to
how many carry bits are generated by the carry-tree.
Generating every carry bit is called sparsity-1, whereas
generating every other is sparsity-2 and every fourth is sparsity-
4. The resulting carries are then used as the carry-in inputs for
much shorter ripple carry adders or some other adder design,
which generates the final sum bits. Increasing sparsity reduces
the total needed computation and can reduce the amount of
routing congestion.
Figure 5: Sparsity-4 Kogge-Stone adder
Fig. 5 is an example of a Kogge–Stone adder with sparsity-
4. Elements eliminated by sparsity shown marked with
transparency. As shown, power and area of the carry generation
is improved significantly, and routing congestion is
substantially reduced. Each generated carry feeds a multiplexer
for a carry select adder or the carry-in of a ripple carry adder.
16-Bit Sparse Kogge-Stone adder
The Sparse Kogge-Stone adder consists [10] of several
smaller ripple carry adders (RCAs) on its lower half and a carry
tree on its upper half. Thus, the sparse Kogge-Stone adder
terminates with RCAs. The number of carries generated is less
in a Sparse Kogge- Stone adder compared to the regular
Kogge-Stone adder. The functionality of the GP block, black
cell and the gray cell remains exactly the same as in the regular
Figure 6: 16-Bit Sparse Kogge-Stone Adder [6]](https://image.slidesharecdn.com/ijtra1407116-151026143154-lva1-app6892/85/IMPLEMENTATION-OF-128-BIT-SPARSE-KOGGE-STONE-ADDER-USING-VERILOG-2-320.jpg)
![International Journal of Technical Research and Applications e-ISSN: 2320-8163,
www.ijtra.com Volume 2, Issue 4 (July-Aug 2014), PP. 90-92
92 | P a g e
Kogge-Stone adder. The schematic for a 16-bit sparse
Kogge-Stone adder is shown in Fig. 6. Sparse and regular
Kogge-Stone adders have essentially the same delay when
implemented on an FPGA although the former utilizes much
less resources
VI.SIMULATION AND RESULT
I have synthesized 128-Bit Sparse Kogge-Stone adder using
Verilog on ISE Xilinx 10.1 and simulated using MODELSIM
6.4a. Results shows that 128-Bit Sparse Kogge –Stone adder
uses No. of slices-134, No. of 4 inputs LUTs-235, No. of IOBs-
264 and also the delay exerted by Sparse Kogge-Stone adder is
26.543 ns.
Delay exerted by above mentioned adder is less when
compared with the 16-bit RCA and CLA which is 26.686 ns
using Verilog HDL on ISE Xilinx 10.1. Hence while
comparing 128 Bit Kogge-Stone Adder even with the Lower
bit adder such as 16 bit Carry Look ahead adder and 16 bit
Ripple Carry adder in terms of delay, even then it is faster.
Hence its useful in industries.
Device Utilization Summary
TABLE I. DEVICE UTILISATION SUMMARY OF
SPARSE KOGGE-STONE ADDER
Figure 7: RTL Schematic of 128-bit Sparse Kogge-Stone
adder
Figure 8: Waveform of 128- bit S-KSA
REFERENCES
[1] CH. Chimpiraiah, E.V.Vijay, “An Efficient Architecture for
Parallel Adder”, International Journal of VLSI and Embedded
Systems Vol. 03, Issues 04; Sep-Oct 2012.
[2] D.H.K Hoe, C. Martinez, and J.Vundavalli, “Design and
Characterisation of Parallel Prefix Adders using FPGAs”, IEEE
43rd Southern Synopsium on System Theory, March 2011.
[3] Kogge P and Stone H, “A Parallel Algorithm for the Efficient
Solutions of a General Class of Recurrence Relations”, IEEE
Transactions on Computers, Vol. C-22, No.8, 1973.
[4] B Pullarao, J.Parveen Kumar, “ Design of High Speed Based On
Parallel Prefix Adders Using In FPGA”, International
Journal of Engineering Sciences & Research Technology
(IJESRT) Dec, 2013
[5] Pakkiraiah Chakali, Madhu Kumar Patnala,” Design of High
Speed Kogge-Stone Based Carry Select Adder”, International
Journal of Emerging Science and Engineering, Vol.1, Issue-4,
February 2013.
[6] T. Lynch and E. E. Swatzlander, ”A Spanning Tree Carry Look-
Ahead adder”, IEEE Transactions on computers, Vol. 41, no. 8
,pp. 931-939, Aug. 1992.
[7] P.Annapurna Bai, M.Vijaya Laxmi , ”Design of 128-bit Kogge-
Stone Low Power Parallel Prefix Adder for High Speed
Arithmatic Circuits”, International Journal of Engineering and
Technology, Vol.-2,Issue-6, Aug 2013
[8] Andrew Beaumont-Smith and Cheng-Chew Lim, “Parallel
Prefix Adder Design”, Department of Electrical and Electronic
Engineering, the University of Adelaide, 2001. Chris D.
Martinez, L. P. Deepthi Bollepalli, and David H.
[9] K. Hoe, “A Fault Tolerant Parallel-Prefix Adder for VLSI and
FPGA Design”, 44th IEEE Southeastern Symposium on System
Theory, 2012.
[10] K. Vitoroulis and A. J. Al-Khalili,“ Performance of Parallel
Prefix Adders Implemented with FPGA technology”, IEEE
Northeast Workshop on Circuits and Systems, pp. 498-501, Aug.
2007.](https://image.slidesharecdn.com/ijtra1407116-151026143154-lva1-app6892/85/IMPLEMENTATION-OF-128-BIT-SPARSE-KOGGE-STONE-ADDER-USING-VERILOG-3-320.jpg)
IMPLEMENTATION OF 128-BIT SPARSE KOGGE-STONE ADDER USING VERILOG
- 1. International Journal of Technical Research and Applications e-ISSN: 2320-8163, www.ijtra.com Volume 2, Issue 4 (July-Aug 2014), PP. 90-92 90 | P a g e IMPLEMENTATION OF 128-BIT SPARSE KOGGE-STONE ADDER USING VERILOG Geeta Rani1, Sachin Kumar2 1 M.Tech Student, 2 Faculty Department of Electronics & Communication M. Tech Student MERI COLLEGE OF ENGINEERING & TECHNOLOGY Sampla Abstract— Parallel Prefix adders have been one of the most notable among several designs proposed in the past. The advantage of utilizing the flexibility in implementing these structures based upon through put requirements. Due to continuing integrating intensity and the growing needs of portable devices, low power and high performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this proposed system, Kogge-Stone adder which is one of types of parallel prefix adder is used. Kogge stone is the fastest adder because of its minimum fan-out. When parallel prefix adder is compared with classical adders it is advantageous in every aspect. The study reveals that Parallel Prefix adder has the least power delay product when compared with its peer existing adder structures (Ripple carry adder, Carry save adders etc). Simulation results are verified using Xilinx 10.1 and MODELSIM 6.4a softwares. Key words— Carry Tree Adder, Kogge-Stone Adder, Sparse Kogge-Stone Adder. I.INTRODUCTION Arithmatic operations i.e. addition, multiplication are common in digital circuits. Binary adders are most basic and widely used arithmetic operations and play a vital role in determining the performance of a design. The basic need from the circuit is that it has less computational time and is of small size. Adders when we talk about adders what we think most probably person will think that it is a device that can add two or more numbers. It is perfectly correct definition. However we just discuss here about digital adders. Adder is a digital circuit that uses in computers and in processors as in there arithmetic and logic unit as well in other parts of processor that use to calculate addresses table indices and other similar operations. Most common adders operate on binary numbers. Basically adders are of two types: Half adder and Full adder. Two half adders can construct one full adder and full adder further construct many complex adders such as ripple carry adder, carry look-ahead adder and carry select adder etc. Basic adders were the slow one. Generally Ripple carry adder (parallel adder) was used to carry out binary addition. Many researches done over several years to find a suitable technique for parallel adders so that delay [1] can be minimized, performance can be better. Hence to reduce the computation time, engineers proposed faster ways by using Carry Look-Ahead (CLA) adder. It uses the parallel prefix operation. In this paper, one of parallel prefix adder is discussed. II.CARRY-TREE ADDER Carry tree adder is also known as the Parallel-Prefix adder. In tree adders, carries are [2] generated in parallel and fast computation is obtained at the expense of increased area and power. The main advantage of the design is that the carry tree [6] reduces the number of logic levels (N) by essentially generating the carries in parallel. III.EXISTING PARALLEL PREFIX ADDERS The prominent parallel prefix tree adders, that are invented so far are, Kogge-Stone, Brent-Kung, Han-Carlson, and Sklansky. There exists various architectures fro carry calculation part. Tradeoff in these architecture involves: Area of adder Its depth The fan-out of the nodes The overall wiring network. Out of these, it was found from the literature that Kogge- stone adder is the fastest adder when compared to other adders. Kogge-Stone adder implementation [7] is most straightforward, and also it has one of the shortest critical paths of all tree adders. The drawback with the Kogge-Stone adder implementation is the large area consumed and the more complex routing (Fan-Out) of interconnects. The two signals that are generated during various stages: Propagate: controls whether a carry is propagated from lower bits to higher bits. Generate: controls whether a carry is generated. Figure 1: Three stage structure for carry tree adder Fig.1 is the three stage structure for carry tree adder. As there are three stages in parallel [5] prefix adder, below is the description of stages: 1. Pre-processing: Generate(Pi, Gi) from Ai, Bi) Pi = Ai ⨁ Bi ………(1) Gi = Ai . Bi ………(2) 2. Carry look-Ahead network: Generate (Pij, Gij) from (Gi, Pi) and (Gj, Pj) [5] Pi:j = Pi:k+1 . Pk:j …………(3) Gi:j = Gi:k+1 | (pi:k+1 . Gk …………(4)
- 2. International Journal of Technical Research and Applications e-ISSN: 2320-8163, www.ijtra.com Volume 2, Issue 4 (July-Aug 2014), PP. 90-92 91 | P a g e 3. Post processing: Sumi = Pi ⨁ Carryi-1 ………(5) Ci = Gi:0 or (Cin and pi:0) ………(6) IV.KOGGE-STONE ADDER The Kogge-Stone adder concept [3] was developed by Peter M. Kogge and Harold S. Stone, which they published in 1973 in a seminal paper titled “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations”. First the focus is on the Kogge-Stone adder has minimal logic depth and fan-out. The number of stages are log N, fan-out 2 at each stage and have long wires. Fig. 2 & 3 are the Black cell and grey cells description. Figure 2(a): Schematic of Black cell Figure 2(b): Symbol of Black cell Figure 3(a): Schematic of Grey cell Figure 3(b): Symbol of Grey cell Kogge-stone adder design: Step 1: First to generate propagation and generation signals for each bit. [9] Step 2: to generate black cell and grey cell equations. Step 3: in each step grey cell generated. Step 4: By using grey cell equation to generate the carry bits directly. Step 5: To combine Propagation and carry bits for each step to generate sum. Fig. 4 gives the 16-Bit Kogge-Stone adder. Figure 4: 16-bit Kogge-Stone Adder V.SPARSE KOGGE-STONE ADDER Enhancements to the original implementation include increasing the radix and sparsity of the adder. The radix of the adder refers to how many results from previous level of computation are used to generate the next one. Doing so increases the power and delay of each stage, but reduces the number of required stages. The sparsity of the adder refers to how many carry bits are generated by the carry-tree. Generating every carry bit is called sparsity-1, whereas generating every other is sparsity-2 and every fourth is sparsity- 4. The resulting carries are then used as the carry-in inputs for much shorter ripple carry adders or some other adder design, which generates the final sum bits. Increasing sparsity reduces the total needed computation and can reduce the amount of routing congestion. Figure 5: Sparsity-4 Kogge-Stone adder Fig. 5 is an example of a Kogge–Stone adder with sparsity- 4. Elements eliminated by sparsity shown marked with transparency. As shown, power and area of the carry generation is improved significantly, and routing congestion is substantially reduced. Each generated carry feeds a multiplexer for a carry select adder or the carry-in of a ripple carry adder. 16-Bit Sparse Kogge-Stone adder The Sparse Kogge-Stone adder consists [10] of several smaller ripple carry adders (RCAs) on its lower half and a carry tree on its upper half. Thus, the sparse Kogge-Stone adder terminates with RCAs. The number of carries generated is less in a Sparse Kogge- Stone adder compared to the regular Kogge-Stone adder. The functionality of the GP block, black cell and the gray cell remains exactly the same as in the regular Figure 6: 16-Bit Sparse Kogge-Stone Adder [6]
- 3. International Journal of Technical Research and Applications e-ISSN: 2320-8163, www.ijtra.com Volume 2, Issue 4 (July-Aug 2014), PP. 90-92 92 | P a g e Kogge-Stone adder. The schematic for a 16-bit sparse Kogge-Stone adder is shown in Fig. 6. Sparse and regular Kogge-Stone adders have essentially the same delay when implemented on an FPGA although the former utilizes much less resources VI.SIMULATION AND RESULT I have synthesized 128-Bit Sparse Kogge-Stone adder using Verilog on ISE Xilinx 10.1 and simulated using MODELSIM 6.4a. Results shows that 128-Bit Sparse Kogge –Stone adder uses No. of slices-134, No. of 4 inputs LUTs-235, No. of IOBs- 264 and also the delay exerted by Sparse Kogge-Stone adder is 26.543 ns. Delay exerted by above mentioned adder is less when compared with the 16-bit RCA and CLA which is 26.686 ns using Verilog HDL on ISE Xilinx 10.1. Hence while comparing 128 Bit Kogge-Stone Adder even with the Lower bit adder such as 16 bit Carry Look ahead adder and 16 bit Ripple Carry adder in terms of delay, even then it is faster. Hence its useful in industries. Device Utilization Summary TABLE I. DEVICE UTILISATION SUMMARY OF SPARSE KOGGE-STONE ADDER Figure 7: RTL Schematic of 128-bit Sparse Kogge-Stone adder Figure 8: Waveform of 128- bit S-KSA REFERENCES [1] CH. Chimpiraiah, E.V.Vijay, “An Efficient Architecture for Parallel Adder”, International Journal of VLSI and Embedded Systems Vol. 03, Issues 04; Sep-Oct 2012. [2] D.H.K Hoe, C. Martinez, and J.Vundavalli, “Design and Characterisation of Parallel Prefix Adders using FPGAs”, IEEE 43rd Southern Synopsium on System Theory, March 2011. [3] Kogge P and Stone H, “A Parallel Algorithm for the Efficient Solutions of a General Class of Recurrence Relations”, IEEE Transactions on Computers, Vol. C-22, No.8, 1973. [4] B Pullarao, J.Parveen Kumar, “ Design of High Speed Based On Parallel Prefix Adders Using In FPGA”, International Journal of Engineering Sciences & Research Technology (IJESRT) Dec, 2013 [5] Pakkiraiah Chakali, Madhu Kumar Patnala,” Design of High Speed Kogge-Stone Based Carry Select Adder”, International Journal of Emerging Science and Engineering, Vol.1, Issue-4, February 2013. [6] T. Lynch and E. E. Swatzlander, ”A Spanning Tree Carry Look- Ahead adder”, IEEE Transactions on computers, Vol. 41, no. 8 ,pp. 931-939, Aug. 1992. [7] P.Annapurna Bai, M.Vijaya Laxmi , ”Design of 128-bit Kogge- Stone Low Power Parallel Prefix Adder for High Speed Arithmatic Circuits”, International Journal of Engineering and Technology, Vol.-2,Issue-6, Aug 2013 [8] Andrew Beaumont-Smith and Cheng-Chew Lim, “Parallel Prefix Adder Design”, Department of Electrical and Electronic Engineering, the University of Adelaide, 2001. Chris D. Martinez, L. P. Deepthi Bollepalli, and David H. [9] K. Hoe, “A Fault Tolerant Parallel-Prefix Adder for VLSI and FPGA Design”, 44th IEEE Southeastern Symposium on System Theory, 2012. [10] K. Vitoroulis and A. J. Al-Khalili,“ Performance of Parallel Prefix Adders Implemented with FPGA technology”, IEEE Northeast Workshop on Circuits and Systems, pp. 498-501, Aug. 2007.