![PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
ADD TOP = C+D
MUL
TOP =
(C+D)*(A+B)
POP X M[X] = TOP](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-3-320.jpg)
![LOAD A AC = M[A]
ADD B AC = AC + M[B]
STORE T M[T] = AC
LOAD C AC = M[C]
ADD D AC = AC + M[D]
MUL T AC = AC * M[T]
STORE X M[X] = AC](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-5-320.jpg)
![MOV R1, A R1 = M[A]
ADD R1, B R1 = R1 + M[B]
MOV R2, C R2 =M[C]
ADD R2, D R2 = R2 + M[D]
MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-7-320.jpg)
![Three Address Instruction
The format of a three address instruction requires three operand fields.
These three fields can be either memory addresses or registers.
Two processor registers, R1 and R2.
The operand1 and operand2 contain the data or address that the CPU will
operate. Operand 3 contains the result’s address.
ADD R1, A, B R1 M [A] + M [B]
←
ADD R2, C, D R2 M [C] + M [D]
←
MUL X, R1, R2 M [X] R1 R2
← ∗](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-8-320.jpg)
![4. Direct Addressing Mode-
In this addressing mode,
• The address field of the instruction contains the effective address of the
operand.
• Only one reference to memory is required to fetch the operand.
• It is also called as absolute addressing mode.
• Example-
•ADD X will increment the value stored in the accumulator by the value stored at memory location X.
AC AC + [X]
←](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-14-320.jpg)
![5. Indirect Addressing Mode-
In this addressing mode,
• The address field of the instruction specifies the address of memory location that
contains the effective address of the operand.
• Two references to memory are required to fetch the operand.
Example-
• ADD X will increment the value stored in the accumulator by the value stored at
memory location specified by X.
AC ← AC + [[X]]](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-15-320.jpg)
![6. Register Direct Addressing Mode-
The operand is contained in a register set.
• The address field of the instruction refers to a CPU register that contains the operand.
• No reference to memory is required to fetch the operand.
• This addressing mode is similar to direct addressing mode.
• The only difference is address field of the instruction refers to a CPU register instead of
main memory.
Example-
•ADD R will increment the value stored in the accumulator
by the content of register R.
AC ← AC + [R]](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-16-320.jpg)
![ The PUSH operation is implemented with the following sequence of micro
operations:
1. SP SP+1 increment stack pointer
2. M[SP] DR write item on top of stack.
if(SP=0) then (FULL 1) check if stack is full .
EMPTY 0 mark the stack not empty](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-28-320.jpg)
![ The POP operation is implemented with the following sequence of micro
operations:
DR M[SP] read item from top of the stack
2. SP SP-1 decrement stack pointer
3. if(SP=0) then (EMPTY 1) check if stack is empty
4. FULL 0 mark the stack not full](https://image.slidesharecdn.com/instructionformats-241117152715-721ac30f/85/Instruction-Formats-in-computer-architecture-pptx-29-320.jpg)
Instruction Formats in computer architecture.pptx
- 1. Instruction Formats The instruction format contains opcode (the instructions to be executed), operand (the data on which the instructions are to be executed), and addressing mode. The instruction format is depicted in a rectangular box, symbolizing the instruction bits in memory words or a control register. The bits grouped are divided into three parts: Instruction format is defined as machine instruction format that CPU can directly decode and execute TYPES OF INSTRUCTION FORMATS • One Address Instruction Format. This instruction format uses only one address field. The other operand is stored on Accumulator Register. • Two Address Instruction Format. It uses two address fields. • Three Address Instruction Format. It uses three instruction fields.
- 2. ZERO ADDRESS INSTRUCTION This instruction does not have an operand field, and the location of operands is implicitly represented. Example: Consider the below operations, which shows how X = (A + B) (C ∗ + D) expression will be written for a stack-organized computer.
- 3. PUSH A TOP = A PUSH B TOP = B ADD TOP = A+B PUSH C TOP = C PUSH D TOP = D ADD TOP = C+D MUL TOP = (C+D)*(A+B) POP X M[X] = TOP
- 4. One Address Instruction This instruction uses an implied accumulator for data manipulation operations. An accumulator is a register used by the CPU to perform logical operations. In one address instruction, the accumulator is implied, and hence, it does not require an explicit reference. For multiplication and division, there is a need for a second register. However, here we will neglect the second register and assume that the accumulator contains the result of all the operations. This instruction format has only one operand field. This address field uses two special instructions to perform data transfer, namely: • LOAD: This is used to transfer the data to the accumulator. • STORE: This is used to move the data from the accumulator to the memory.
- 5. LOAD A AC = M[A] ADD B AC = AC + M[B] STORE T M[T] = AC LOAD C AC = M[C] ADD D AC = AC + M[D] MUL T AC = AC * M[T] STORE X M[X] = AC
- 6. TWO ADDRESS INSTRUCTION This instruction is most commonly used in commercial computers. This address instruction format has three operand fields. The two address fields can either be memory addresses or registers. The MOV instruction transfers the operands to the memory from the processor registers. R1, R2 registers
- 7. MOV R1, A R1 = M[A] ADD R1, B R1 = R1 + M[B] MOV R2, C R2 =M[C] ADD R2, D R2 = R2 + M[D] MUL R1, R2 R1 = R1 * R2 MOV X, R1 M[X] = R1
- 8. Three Address Instruction The format of a three address instruction requires three operand fields. These three fields can be either memory addresses or registers. Two processor registers, R1 and R2. The operand1 and operand2 contain the data or address that the CPU will operate. Operand 3 contains the result’s address. ADD R1, A, B R1 M [A] + M [B] ← ADD R2, C, D R2 M [C] + M [D] ← MUL X, R1, R2 M [X] R1 R2 ← ∗
- 9. ADDRESSING MODES The operation field of an instruction specifies the operation to be performed. This operation will be executed on some data which is stored in computer registers or the main memory. The way any operand is selected during the program execution is dependent on the addressing mode of the instruction. The purpose of using addressing modes is as follows: 1. To give the programming versatility to the user. 2. To reduce the number of bits in addressing field of instruction.
- 11. 1. Implied Addressing Mode- • The definition of the instruction itself specify the operands implicitly. • It is also called as implicit addressing mode. Examples- • The instruction “Complement Accumulator” is an implied mode instruction. • In a stack organized computer, Zero Address Instructions are implied mode instructions
- 12. 2. Stack Addressing Mode- In this addressing mode, • The operand is contained at the top of the stack. Example- ADD • This instruction simply pops out two symbols contained at the top of the stack. • The addition of those two operands is performed. • The result so obtained after addition is pushed again at the top of the stack
- 13. 3. Immediate Addressing Mode- In this addressing mode, • The operand is specified in the instruction explicitly. • Instead of address field, an operand field is present that contains the operand. Examples- •ADD 10 will increment the value stored in the accumulator by 10. •MOV R #20 initializes register R to a constant value 20.
- 14. 4. Direct Addressing Mode- In this addressing mode, • The address field of the instruction contains the effective address of the operand. • Only one reference to memory is required to fetch the operand. • It is also called as absolute addressing mode. • Example- •ADD X will increment the value stored in the accumulator by the value stored at memory location X. AC AC + [X] ←
- 15. 5. Indirect Addressing Mode- In this addressing mode, • The address field of the instruction specifies the address of memory location that contains the effective address of the operand. • Two references to memory are required to fetch the operand. Example- • ADD X will increment the value stored in the accumulator by the value stored at memory location specified by X. AC ← AC + [[X]]
- 16. 6. Register Direct Addressing Mode- The operand is contained in a register set. • The address field of the instruction refers to a CPU register that contains the operand. • No reference to memory is required to fetch the operand. • This addressing mode is similar to direct addressing mode. • The only difference is address field of the instruction refers to a CPU register instead of main memory. Example- •ADD R will increment the value stored in the accumulator by the content of register R. AC ← AC + [R]
- 17. 7. Register Indirect Addressing Mode- In this addressing mode, • The address field of the instruction refers to a CPU register that contains the effective address of the operand. • Only one reference to memory is required to fetch the operand. • This addressing mode is similar to indirect addressing mode. • The only difference is address field of the instruction refers to a CPU register
- 18. Relative Addressing Mode- In this addressing mode, • Effective address of the operand is obtained by adding the content of program counter with the address part of the instruction. Effective Address= Content of Program Counter + Address part of the instruction • Program counter (PC) always contains the address of the next instruction to be executed. • After fetching the address of the instruction, the value of program counter immediately increases. • The value increases irrespective of whether the fetched instruction has completely executed or not.
- 19. Indexed Addressing Mode- In this addressing mode, • Effective address of the operand is obtained by adding the content of index register with the address part of the instruction. Effective Address = Content of Index Register + Address part of the instruction
- 20. Base Register Addressing Mode- In this addressing mode, • Effective address of the operand is obtained by adding the content of base register with the address part of the instruction. Effective Address= Content of Base Register + Address part of the instruction
- 21. Auto-Increment Addressing Mode- This addressing mode is a special case of Register Indirect Addressing Mode where- Effective Address of the Operand = Content of Register • After accessing the operand, the content of the register is automatically incremented by step size ‘d’. • Step size ‘d’ depends on the size of operand accessed. • Only one reference to memory is required to fetch the operand.
- 22. In auto-increment addressing mode, • First, the operand value is fetched. • Then, the instruction register RAUTO value is incremented by step size ‘d’.
- 23. Auto-Decrement Addressing Mode- This addressing mode is again a special case of Register Indirect Addressing Mode where,-Effective Address of the Operand= Content of Register – Step Size In this addressing mode, • First, the content of the register is decremented by step size ‘d’. • Step size ‘d’ depends on the size of operand accessed. • After decrementing, the operand is read. • Only one reference to memory is required to fetch the operand.
- 24. Here, •First, the instruction register RAUTO will be decremented by 2. •Then, updated value of RAUTO will be 3302 – 2 = 3300. •At memory address 3300, the operand will be found. First, the instruction register RAUTO value is decremented by step size ‘d’. •Then, the operand value is fetched.
- 25. A stack is a storage device that stores information in such a manner that the item stored last is the first item to be retrieved. The stack in digital computers is essentially a memory unit with an address register that can count. The register that holds the address for the stack is the stack pointer (SP) that points to the top of stack. The operations like push and pop are performed by incrementing or decrementing the SP
- 27. A stack can be placed in a portion of a large memory or it can be organized as a collection of finite number of memory words or registers. Consider a stack of 64 words. The SP contains a binary number whose value is equal to the address of the word that is currently on top of the stack. Three items are placed in the stack: A, B, C in that order. C is on top of the stack so that the content of SP is now 3. To remove the top item, the stack is popped by reading the memory word at address 3 and decrementing the content of SP. Item B is now on top of the stack since SP holds address 2.To insert a new item, the stack is pushed by incrementing SP and writing a word in the next-higher location in the stack.
- 28. The PUSH operation is implemented with the following sequence of micro operations: 1. SP SP+1 increment stack pointer 2. M[SP] DR write item on top of stack. if(SP=0) then (FULL 1) check if stack is full . EMPTY 0 mark the stack not empty
- 29. The POP operation is implemented with the following sequence of micro operations: DR M[SP] read item from top of the stack 2. SP SP-1 decrement stack pointer 3. if(SP=0) then (EMPTY 1) check if stack is empty 4. FULL 0 mark the stack not full