Introduction to CPLD: Field Programmable Gate Array
- 1. Unit-V Introduction to PLDs Dr. Sk. Enaul Haq Professor, Department of ECE, VVIT VLSI Design
- 2. Introduction Logic devices can be classified into two broad categories: i. fixed and ii. Programmable Circuits in a fixed logic device are permanent: they perform one function or set of functions, and once manufactured, they cannot be changed Eg: ASIC (Application Specific Integrated Circuit) – IC 7400 (NAND gate IC) 74381 (4-BIT ALU) Programmable logic devices (PLDs) are standard, off the- shelf parts that can be modified at any time to perform any number of functions Eg: PLA, PAL Programmable AND and OR Gate Arrays Programmable AND Gate Arrays Fixed OR Gate Arrays PLA PAL
- 3. Introduction • A key benefit of using PLDs is that during the design phase designers can change the circuitry as often as they want until the design operates satisfactorily • PLDs are based on rewritable memory technology: to modify the design, the device only needs to be reprogrammed • Reusability is a further attractive feature of PLDs • Many types of programmable logic devices are currently available • The range of market products includes small devices capable of implementing a handful of logic equations up to huge FPGAs that can hold an entire processor core plus a number of peripherals • Within programmable logic devices, two major types deserve to be highlighted: i. the complex programmable logic device (CPLD) and ii. field programmable gate array (FPGA) • As chip densities increased, PLD manufacturers naturally developed their products toward larger parts, called complex programmable logic devices (CPLDs)
- 4. COMPLEX PROGRAMMABLE LOGIC DEVICES • CPLD contains a bunch of PLD blocks whose inputs and outputs are connected together by a global interconnection matrix • A CPLD is an arrangement of many SPLD-like blocks on a single chip • These circuit blocks might be either PAL-like or PLA-like blocks • Thus a CPLD has two levels of programmability: each PLD block can be programmed, and then the interconnections between the PLDs can be programmed. Characteristics: i. They have a higher input to logic gate ratio. ii. These devices are denser than SPLDs but have better functional abilities. iii. CPLDs are based on EPROM or EEPROM technology. iv. If you require a larger number of macrocells for a given application, ranging anywhere between 32 to 1000 macrocells, then a Complex Programmable Logic Device is the solution. v. We use CPLD in applications involving larger I/Os, but data processing is relatively low.
- 5. COMPLEX PROGRAMMABLE LOGIC DEVICES
- 6. Field Programmable Gate Array (FPGA) • Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects • FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing • This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks • FPGAs used to be selected for lower speed/complexity/volume designs in the past, today’s FPGAs easily push the 500 MHz performance barrier • With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price points, FPGAs are a compelling proposition for almost any type of design
- 7. Applications of FPGA • Usually, FPGAs are kept for particular vertical applications where the production volume is small • Today, the new performance dynamics and cost have extended the range of viable applications • Some More Common FPGA Applications are: Aerospace and Defense, Medical Electronics, ASIC Prototyping, Audio, Automotive, Broadcast, Consumer Electronics, Distributed Monetary Systems, Data Center, High Performance Computing, Industrial, Medical, Scientific Instruments, Security systems, Video & Image Processing, Wired Communications
- 8. Basic Architecture of FPGA • The basic FPGA architecture consists of a two dimensional array of logic blocks and flip-flops with means for the user to configure (i) the function of each logic blocks, (ii) the inputs/outputs, and (iii) the interconnection between blocks • These Logic Blocks are connected with each other, and with I/O lines or blocks through interconnection lines (switch box consists of these connections) Figure: Basic architecture of FPGA: two-dimensional array of programmable logic cells, interconnections, and input/ouput Switch Box Vertical Channel Horizontal Channel
- 9. Basic Architecture of FPGA Configurable Logic Block (CLB) • An FPGA CLB can be designed with a LUT, typically a 4-input LUT, implementing a combinational logic function, and a register that optionally stores the output of the logic generator • Logic blocks that carry out logical functions are look-up tables (LUTs) A Simple Configurable Logic Block 2:1 MUX
- 10. Basic Architecture of FPGA Look-Up Tables • The way logic functions are implemented in a FPGA is another key feature • Logic blocks that carry out logical functions are look-up tables (LUTs), implemented as memory, or multiplexer and memory • An n-bit LUT consists of two parts, i. Memory (Vertical array of 2^n Latches ), and ii. Multiplexer 2-LUT consists of 4x1 Memory (4 Latches) and 4X1 Multiplexer 4 Latches ( 4 x 1 Memory) 4 x 1 Multiplexer
- 11. Basic Architecture of FPGA Look-Up Tables • Using an n-bit LUT, an n-variable logic function can be implemented • All the 2-input logic gates or 2-variable functions can be implemented using the 2-bit LUT given below • Select lines of the Multiplexer are the input variables, and the bit stream to be stored in the Memory is the output bit sequence of all the possible input combinations (Example: 2-input AND gate is shown below) A B F 0 0 0 1 AND gate o/p
- 12. Basic Architecture of FPGA Implementation of 2-variable functions using Look-Up Tables • Implement F = AB + A’B using LUT
- 13. Basic Architecture of FPGA Implementation of 4-variable functions using Look-Up Tables • Implement F = A’B’C + A’BC’ + ABC’ + ABC using LUT Solution: F can be given as F = Ʃm(1,5,6,7) As it is a 3-variable function, 3-LUT is required and it consists of 8x1 Memory and 8:1 MUX A B C F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1
- 14. Basic Architecture of FPGA Implementation of functions using Look-Up Tables (Exercise) • Implement Full adder using LUT • Implement F = Ʃm(0,1,4,5,8,9,11,14,15) using LUT
- 15. Programmable Interconnection • To allow for flexible interconnection of CLBs, FPGAs have 3 programmable routing resources: 1. Vertical and horizontal routing channels which consist of different length wires that can be connected together if needed. These channel run vertically and horizontally between columns and rows of CLBs as shown in the Figure. 2. Connection boxes, which are a set of programmable links that can connect input and output pins of the CLBs to wires of the vertical or the horizontal routing channels. 3. Switch boxes, located at the intersection of the vertical and horizontal channels. • These are a set of programmable links that can connect wire segments in the horizontal and vertical channels. • Most widely used interconnection method is SRAM based connection
- 16. Programmable Interconnection SRAM based Programming Technology • FPGA connections are achieved using pass-transistors, transmission gates, or multiplexers that are controlled by SRAM cells • This technology allows fast in-circuit reconfiguration • The major disadvantages are the size of the chip, required by the RAM • technology, and the needs of some external source (usually external nonvolatile memory chips) to load the chip configuration. • The FPGA can be programmed an unlimited number of times SRAM connection
- 17. Programmable Interconnection SRAM Programming Technology Switch Box: It is a junction of horizontal and vertical interconnecting wires wherein the connections are made by using pass transistors and SRAM cells Switch Box Connection of wires through SRAM cells & pass transistors in Switch Box Programming the interconnections by writing SRAM cells
- 18. Programmable I/O Blocks • The I/O pads on an FPGA are connected to programmable input/output blocks, which facilitate connecting the signals from FPGA logic blocks to the external world in desired forms and formats. I/O blocks on modern FPGAs allow use of the pin as input and/or output, in direct (combinational) or latched forms, in tristate true or inverted forms, and with a variety of I/O standards. Figure below shows an example configurable input/output block (I/OB). Each I/OB has a number of I/O options, which can be selected by configuration memory cells, indicated by boxes with an “M.” The I/O pad can be programmed to be an output or an input. To use the cell as an output, the tristate buffer must be enabled. To use the cell as an input, the tristate control must be set to place the tristate buffer, which drives the output pin, in the high-impedance state.
- 19. Example on the implementation of a logic function using FPGA • Use an FPGA with 2 input LUTS to implement the function, f = x1·x3·x6' + x1·x4·x5·x6' + x2·x3·x7 + x2·x4·x5·x7 • Factor f to get sub-expressions with max fan-in = 2 f = x1·x6'· (x3 + x4·x5) + x2·x7(x3 + x4·x5) = (x1·x6' + x2·x7)(x3 + x4·x5)
- 20. Programming Technologies • Families of FPGAs differ from each other by the physical means for implementing user programmability, arrangement of interconnection wires, and basic functionality of the logic blocks • There are three types of Programming Methods i. SRAM based ii. Antifuse based, and iii. EPROM based
- 21. Programming Technologies SRAM based Programming Technology • FPGA connections are achieved using pass-transistors, transmission gates, or multiplexers that are controlled by SRAM cells • This technology allows fast in-circuit reconfiguration • The major disadvantages are the size of the chip, required by the RAM • technology, and the needs of some external source (usually external nonvolatile memory chips) to load the chip configuration. • The FPGA can be programmed an unlimited number of times SRAM connection
- 22. Programming Technologies SRAM Programming Technology Switch Box: It is a junction of horizontal and vertical interconnecting wires wherein the connections are made by using pass transistors and SRAM cells Switch Box Connection of wires through SRAM cells & pass transistors in Switch Box Programming the interconnections by writing SRAM cells
- 23. Programming Technologies Antifuse Programming Technology • An antifuse remains in a high-impedance state until it is programmed into a low-impedance or “fused” state • This technology can be used only once on one-time programmable (OTP) devices • It is less expensive than the RAM technology
- 24. Programming Technologies Antifuse Programming Technology • An antifuse is positioned between two interconnect wires and physically consists of three sandwiched layers: the top and bottom layers are conductors, and the middle layer is an insulator • When unprogrammed, the insulator isolates the top and bottom layers, but when programmed the insulator changes to become a low-resistance link
- 25. Programming Technologies EPROM Programming Technology • This method is the same as that used in EPROM/EEPROM memories. The configuration is stored within the device, that is, without external memory • Generally, in-circuit reprogramming is not possible • It is consists of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits • Once programmed, an EPROM can be erased by exposing it to strong ultraviolet light source Advantages 1.Reprogrammable 2.Non volatile Disadvantages 1.Power consumption is high 2.UV exposure is needed to reprogram