Introduction to stm32-part1
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This document introduces the STM32 microcontroller. It will cover the ARM Cortex processor, the STM32 system-on-chip, and its basic building blocks. The course outline includes introductions to the Cortex architecture, CMSIS standard, STM32 system architecture, peripherals, low power operation, safety features, flash memory, and development tools.
Introduction to stm32-part1
- 2. Course Objective After completing this course, you will answer: What is ARM Cortex Processor? What is the STM32 SoC? What are STM32 building blocks? Amr Ali Abdel-Naby@2011 Introduction to STM32
- 3. Course Notes Set your cell phone to vibrate. I assume you know computer architecture. Ask any time. Amr Ali Abdel-Naby@2011 Introduction to STM32
- 4. Course References The Definitive Guide to the ARM Cortex-M3, 2 nd Edition www.arm.com www.st.com/stm32 www.doulos.com Amr Ali Abdel-Naby@2011 Introduction to STM32
- 5. Course Outline Introduction Cortex Overview CMSIS STM32 System Architecture Peripherals Low Power Operation Safety Features The Flash Module Development Tools Amr Ali Abdel-Naby@2011 Introduction to STM32
- 6. Course Outline Introduction Cortex Overview CMSIS STM32 System Architecture Peripherals Low Power Operation Safety Features The Flash Module Development Tools Amr Ali Abdel-Naby@2011 Introduction to STM32
- 7. CPU, Processor, and SoC Amr Ali Abdel-Naby@2011 Introduction to STM32
- 8. About ARM ARM = Advanced/Acorn RISC Machine Founded in 1990 CPU IPs, physical IPs, compilers, SoC infrastructure… Dominates 75% of embedded market Amr Ali Abdel-Naby@2011 Introduction to STM32
- 9. ARM Customers IDMs/IC vendors like: Amr Ali Abdel-Naby@2011 Introduction to STM32
- 10. ARM Overview Amr Ali Abdel-Naby@2011 Introduction to STM32
- 11. ARM by Architecture Amr Ali Abdel-Naby@2011 Introduction to STM32
- 12. ARM Application Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
- 13. ARM Embedded Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
- 14. ARM Secure/Specialities Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
- 15. About ST Microelectronics Merge of SG Microelectronica and Thomson Semiconductors Founded in 1987 ICs, smart cards, microcontrollers… Amr Ali Abdel-Naby@2011 Introduction to STM32
- 16. Course Outline Introduction Cortex Overview CMSIS STM32 System Architecture Peripherals Low Power Operation Safety Features The Flash Module Development Tools Amr Ali Abdel-Naby@2011 Introduction to STM32
- 17. What is Cortex? Next generation ARM Processor Consists of: Classic CPU(s) System peripherals 3 series: A series: for complex applications and OS R series: for real-time systems M series: optimized for cost/power sensitive systems 15 performance levels: 0 lowest Amr Ali Abdel-Naby@2011 Introduction to STM32
- 18. Cortex CPU 32-bit RISC 16 registers 3 stages pipeline with branch prediction Load-store architecture Amr Ali Abdel-Naby@2011 Introduction to STM32
- 19. CPU Operating Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 20. Thumb-2 Instruction Set 32-bit performance with 16-bit code density Need for non ANSI-C is minimum Amr Ali Abdel-Naby@2011 Introduction to STM32
- 21. Memory Map Amr Ali Abdel-Naby@2011 Introduction to STM32
- 22. Unaligned Memory Access Amr Ali Abdel-Naby@2011 Introduction to STM32
- 23. Bit Banding Amr Ali Abdel-Naby@2011 Introduction to STM32
- 24. Buses Code and Data buses Harvard architecture System bus Cortex control space Private peripheral bus On-chip debug system Bus matrix Connects the 1 st 3 buses to the external world Bus arbiters Amr Ali Abdel-Naby@2011 Introduction to STM32
- 25. System Timer 24-bit down counter Auto-reload and end of count interrupt Provide timer tick for OS Has 3 registers: Control & status Enable, select clock source… Reload value Current value Both reload and current registers should be initialized with period Amr Ali Abdel-Naby@2011 Introduction to STM32
- 26. Nested Vector Interrupt Controller Very low deterministic interrupt latency Nested interrupts ANSI C programmed Configurable by manufacture to the needed number of interrupts Amr Ali Abdel-Naby@2011 Introduction to STM32
- 27. NVIC Exception Entry and Exit Amr Ali Abdel-Naby@2011 Introduction to STM32
- 28. Handling Multiple Interrupts A HPI preempts a LPI (12 cycles needed) 6 cycles are needed to fetch new ISR address Tail chaining ensures minimum delay between interrupts in 3 cases: 2 interrupts raised at same time (6 cycles needed) LPI occurs at HPI exit (7 to 18 cycles needed) HPI occurs during push of LPI (6 cycles needed from HPI occurrence) Amr Ali Abdel-Naby@2011 Introduction to STM32
- 29. NVIC Configure and Usage Done on 3 steps: Configure the exception vector table Configure the NVIC registers Configure the peripherals Amr Ali Abdel-Naby@2011 Introduction to STM32
- 30. Configure the Exception Vector Table Amr Ali Abdel-Naby@2011 Introduction to STM32
- 31. Configure the NVIC Registers Set the priority of the interrupt Enable the interrupt source Internal exceptions are configured using system control and system priority User exceptions are configured using IRQ registers Amr Ali Abdel-Naby@2011 Introduction to STM32
- 32. Power Modes CPU enters sleep mode either by: WFI Wakes by an interrupt Executes an ISR WFE Wakes by an external event line SLEEPONEXT: Puts CPU back in sleep mode after ISR SEVONPEND: An ISR even if disabled can generate an event SLEEPDEEP: Halts peripherals as well like PLL Amr Ali Abdel-Naby@2011 Introduction to STM32
- 33. CoreSight Debug Support Amr Ali Abdel-Naby@2011 Introduction to STM32
- 34. Course Outline Introduction Cortex Overview CMSIS STM32 System Architecture Peripherals Low Power Operation Safety Features The Flash Module Development Tools Amr Ali Abdel-Naby@2011 Introduction to STM32
- 35. What is CMSIS? Cortex Microcontroller Software Interface Standard A vendor independent software layer This will ease porting and reusing of software MISRA compliant Amr Ali Abdel-Naby@2011 Introduction to STM32
- 36. CMSIS Structure Amr Ali Abdel-Naby@2011 Introduction to STM32
- 37. File Structure core_cm3.h Cortex M3 global declarations core_cm3.c Cortex M3 global definitions core_cm3.x are tool independent. <device>.h To be included in application software system_<device>.h Device specific declarations system_<device>.c Device specific definitions Amr Ali Abdel-Naby@2011 Introduction to STM32
Editor's Notes
- #2: * 07/16/96 * ##
- #12: ISA: Instruction Set Architecture VFP: Vector Floating Point Jazelle: Extension to run Java Byte Code on ARM machines ARM ISA: 32-bit instructions Thumb ISA: 16-bit instructions Thumb-2 ISA: ARM + Thumb TrustZone: Security Extensions SIMD: Single Instruction Multiple Data NEON: Advanced SIMD Virtualization: Hardware Virtualization NVIC: Nested Vector Interrupt Controller WIC:Wakeup Interrupt Controller * 07/16/96 * ##
- #13: They can execute complex operating systems. Phones, notebooks, PDAs, DTVs, set-top boxes… * 07/16/96 * ##
- #14: Suitable for real-time behavior of power-sensitive applications Control systems, automotive, white goods… * 07/16/96 * ##
- #15: SIMs, smart cards, electronic IDs, electronic payments… * 07/16/96 * ##
- #19: N: Negative Z: Zero C: Carry V: Overflow Q: Saturated minimum/maximum result T: Thumb mode ICI: Interrupt continuable instruction To support deterministic interrupt latency for multi-cycle instructions IT: If then To support conditional execution (execute or NOP) T: Thumb mode Always set to 1 ISR #: NVIC is integrated with core * 07/16/96 * ##
- #20: Flat mode: Out of reset mode = Thread mode + Privileged Operations + Main Stack * 07/16/96 * ##
- #21: DMIPS = Dhrystone MIPS, free benchmark to compare CPU perfromance * 07/16/96 * ##
- #23: Aligned access (left, classical ARM) allows efficient access of variables without need of software libraries support but can waste up to 25% of variable space. Unaligned access (right, Cortex ARM) makes more efficient use of memory. Cortex supports both modes by hardware! * 07/16/96 * ##
- #24: Bit manipulation without bit banding (left, classical ARM) needed a read, modify, write operations to change a single bit Bit banding manipulation (right, Cortex ARM) uses alias region to add * 07/16/96 * ##
- #28: * 07/16/96 * ##
- #31: Starts at the bottom of the address range at 0x00000004. Address 0x0000000 is used to store initial SP. The exception vector table stores addresses rather than instructions. The 1 st 15 are for the ones used by the Cortex core itself. * 07/16/96 * ##
- #33: WFI: Wait for interrupt WFE: Wait for event * 07/16/96 * ##
- #34: JTAG (classical ARM) only worked when CPU is halted. HW breakpoints are only two. Real-time trace can be supported using an Embedded Trace Module (ETM) at extra cost. CoreSight (Cortex ARM) can work with old JTAG interfaces! Hardware tracers built-in. Up to 8 HW breakpoints. Can debug in sleep modes. Synchronize CPU with timers when halted. * 07/16/96 * ##
- #35: * 07/16/96 * ##
- #37: CPAL is implemented by ARM to access the CPU HW MWAL defined by ARM but adapted by silicon vendors to access the SoC devices. It is not implemented yet. DPAL similar to CAPL but defined and implemented by silicon vendors. They use CAPL internally. * 07/16/96 * ##