IRJET- Effect of Newly Developed Data Security Algorithm on the 128-Bits Plaintext and Study of Resistance to Ciphertext Attacks with Maximum Combinational Path Delay using VHDL
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1) The document proposes a new data security algorithm to encrypt 128-bit plaintext into 128-bit ciphertext for protecting data from unauthorized access. 2) The algorithm uses a bit splitter unit to divide the plaintext into four 32-bit blocks, a functional block to operate on the blocks, bit append unit to concatenate the outputs, and Feistel cipher with two 32-bit keys to perform encryption. 3) Simulation results show the algorithm encrypting plaintext into ciphertext in 8.063ns, making it resistant to various attacks like brute-force, timing, snooping, and statistical attacks. The decryption process follows the reverse order.
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![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 04 | Apr-2018 www.irjet.net p-ISSN: 2395-0072
© 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1653
Step 2: The outputs of bit splitter unit and the hash value are
given to the inputs of the new functional unit (F1) which
produces two outputs each having 32-bits (one output given
for the bit append unit and another input to the input of the
new functional unit). This process is repeated for next three
nos. of Fi where i=2 to 4.The hash value of next Fi is the
output of the previous Fi.
Step 3: The outputs of Fi are appended with the help of bit
append unit which produces 128-bits output.
Step 4: Two 32-bits cipher keys are appended together to
produce 64-bits key output for the Feistel Cipher Unit.
Step 5: Feistel Cipher Unit divides the output of bit append
unit into two halfs (L1 & R1) each having 64-bits. Then, the
XOR operation is performed between L1 and the key. The
output of XOR unit and R1 are swapped using the swapper
unit. Then, the outputs ofthe swapper unit is appendedusing
bit append unit which produces 128-bits Ciphertext output.
This ciphertext output is the desired encrypted data to be
transmitted from the transmittertothereceiverthroughwire
/ wireless medium.
2.2 DECIPHERMENT ALGORITHM:
The algorithm for the decryption process can be written in
the reverse order of the encryption algorithm.
3. SIMULATION RESULT AND DISCUSSION
The VHDL code of the proposed work has been simulated
using Xilinx ISE 9.2i software and the desired results have
been obtained.
The simulation result of the encipherment process is given
as follows:
Fig 2: Simulation result of the encipherment process
The simulation result of the decipherment process is given
as follows:
Fig 3: Simulation result of the decipherment process
4. CONCLUSION
After doing the proposed work, it is concluded that the
work is best suited in the field of data security to provide
protection to the 128-bits original data from unauthorized
access. It is resistant to the brute-force attack, timing attack,
snooping attack, pattern attack, statistical attack which
makes the algorithm more robust. The combinational path
delay of the time required to convert 128-bits plaintext into
128-bits ciphertext is 8.063ns which obtained from the
Xilinx software.
REFERENCES
[1] Dr. Sandeep Tayal, Dr. Nipin Gupta, Dr. Pankaj Gupta,
Deepak Goyal, Monika Goyal, “A Review paper on Network
Security and Cryptography”, Advances in Computational
Sciences and Technology, Volume 10, Number 5,pp. 763-
770,2017.
[2] J. G. Pandey,Aanchal Gurawa, Heena Nehra,A. Karmakar,
“An efficient VLSI architecture for data encryption standard
and itsFPGA implementation”,VLSI SATA,IEEEInternational
Conference,pp.1-5,2016.
[3] W.Stallings,“Cryptography and Network Security”, 2nd
Edition, Prentice Hall.
[4] Douglas L. Perry. “VHDL Programming by Examples”,
TMH.
[5] Soufiane Oukili,Seddik Bri,”FPGA implementationofData
Encryption Standard using time variable permutations”,
International Conference on Microelectronics
(ICM),IEEE,pp.126-129,2015.
[6] Ramadhan J. Mstafa; Khaled M. Elleithy, “A highly secure
video steganography using Hamming code (7, 4)”, Systems,
Applications and Technology Conference (LISAT), IEEE
Conference,pp.1-6,2014.
[7] Ravikumar M.Raypure, Prof. Vinay Keswani,
“Implementation For Data Hiding Using Visual
Cryptography”, IRJET, Volume: 04, Issue: 07, 2017.](https://image.slidesharecdn.com/irjet-v5i4369-190225060543/85/IRJET-Effect-of-Newly-Developed-Data-Security-Algorithm-on-the-128-Bits-Plaintext-and-Study-of-Resistance-to-Ciphertext-Attacks-with-Maximum-Combinational-Path-Delay-using-VHDL-2-320.jpg)
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Simulation based design and analysis of combined effect of various data secur...IRJET Journal 1) The document describes a design for encrypting 128-bit digital data during transmission using modified DES, Hamming code, and an iterated product cipher.
2) The 128-bit data is first encrypted using modified DES, then Hamming encoding is applied, producing a 224-bit encoded output.
3) The 224-bit encoded data is further encrypted using a modified iterated product cipher to produce a final 256-bit encrypted output for transmission.
IRJET- Simulation based design and analysis of combined effect of various ...
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icwet1097
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3) The hybrid approach integrates the AES encryption process within the Feistel network structure of DES, using AES transformations like byte substitution and shift rows within each round of the DES Feistel network. This is intended to strengthen security by combining the advantages of both algorithms while reducing individual weaknesses.
IRJET- A Review on Various Secured Data Encryption Models based on AES Standard
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High Speed Optimized AES using Parallel Processing Implementation
High Speed Optimized AES using Parallel Processing ImplementationIRJET Journal This document presents a proposed optimized implementation of the Advanced Encryption Standard (AES) algorithm using parallel processing for high-speed encryption and decryption. The implementation aims to minimize power consumption and critical path delay. It was designed and simulated using VHDL and implemented on an FPGA chip. Experimental results showed that the proposed AES architecture offers superior performance to existing VLSI architectures in terms of power, throughput, and critical path delay. The architecture supports encryption and decryption of 256-bit keys with a throughput of 0.06 Gbps.
Ci25500508
Ci25500508IJERA Editor The document discusses a novel fault detection scheme for the Advanced Encryption Standard (AES) utilizing composite fields to enhance security against internal defects and fault attacks. It presents a hardware model developed in Verilog, which demonstrates improved efficiency in speed, power, and area through parallel generation of round keys and optimized parity-based fault detection structures. The paper compares both software and hardware implementations of the AES encryption process, outlining the benefits and drawbacks of various cryptographic methods, including symmetric and asymmetric key algorithms.
A04660105
A04660105IOSR-JEN This document describes the implementation of the AES (Advanced Encryption Standard) algorithm using a fully pipelined design on an FPGA. It first provides background on the AES algorithm, including its key components and previous hardware implementations. It then details the proposed fully pipelined design, which implements each of AES's 10 rounds as separate pipeline stages to achieve high throughput. Key generation is also pipelined internally. Simulation results show the design achieves a throughput higher than previous reported implementations.
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Iaetsd an survey of efficient fpga implementation of advanced encryption
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IRJET- Effect of Newly Developed Data Security Algorithm on the 128-Bits Plaintext and Study of Resistance to Ciphertext Attacks with Maximum Combinational Path Delay using VHDL
- 1. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 04 | Apr-2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1652 Effect of newly developed data security algorithm on the 128-bits plaintext and study of resistance to ciphertext attacks with maximum combinational path delay using VHDL Paresh Kumar Pasayat1, Kalpataru Sethi2 1Assistant Professor, Dept. of ETC Engineering, IGIT,Odisha, India 2PG student, Dept. of ETC Engineering, IGIT,Odisha, India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract –The proposed paper focusesmainlyonthehiding of information from the unauthorized access and the novel approach adopted so as to prove the robustness of the data security algorithms. The information consists of 128-bit plaintext which needs to be protected fromthehackerbyusing a newly developed data security algorithm. The algorithm protects the data by performing various operations on the plaintext and the chip codes and obtains a 128-bit ciphertext. The different operations have been achieved with the help of bit splitter unit, bit append unit, xor unit and a dependent functional block. The original data can be retrieved at the receiver end by using reverse cipher unit. The proposed work can be implemented in the banking sector, telecommunication sector and military sector etc. Key Words: Plaintext, Ciphertext, Bit Splitter, Bit ppend, Cipher, Functional Block. 1. INTRODUCTION Due to the lack of confidentiality, integrity and authentication of the information being used bythedifferent organizations, the researchers are playing an importantrole for inventing various data security algorithmstoprotect the information from the unauthorized access. The proposed paper aims to protect 128-bit data by introducing a newly developed data security algorithm. First, 128-bitplaintextis converted into 128-bit ciphertext using two 32-bit chip codesand cipher algorithm. Similarly, the 128-bit ciphertext is converted into 128-bit plaintext by using reverse cipher algorithm. 1.1 Project Model The project describes the flow chart for the proposed project work. Each number in the model signifies the no. of bit in the input and output of each unit. The diagrammatic representation of the proposed work is given as follows: Fig 1: Project Model 2. LOGIC USED IN THE PROPOSED DESIGN The logic used in the proposed design has been described in different steps as follow: 2.1 ENCIPHERMENT ALGORITHM: Step 1: First, 128-bits Original data also know as plaintext is fed to the input of the bit splitter unit which divides the data into four half each having equal no. of bits i.e. 32-bits. 32 128-BITS PLAINTEXT BIT_SPLITTER_UNIT F1 F2 F3 F4 BIT_APPEND_UNIT KEY GENERATION UNIT BIT_SPLITTER_UNIT L1 R1 + BIT_APPEND_UNIT 128-BITS CIPHERTEXT L2 R2 32-BITS32-BITS 32 32 32 32 32 3232 128 64 64 64 64 64 64 H0
- 2. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 04 | Apr-2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1653 Step 2: The outputs of bit splitter unit and the hash value are given to the inputs of the new functional unit (F1) which produces two outputs each having 32-bits (one output given for the bit append unit and another input to the input of the new functional unit). This process is repeated for next three nos. of Fi where i=2 to 4.The hash value of next Fi is the output of the previous Fi. Step 3: The outputs of Fi are appended with the help of bit append unit which produces 128-bits output. Step 4: Two 32-bits cipher keys are appended together to produce 64-bits key output for the Feistel Cipher Unit. Step 5: Feistel Cipher Unit divides the output of bit append unit into two halfs (L1 & R1) each having 64-bits. Then, the XOR operation is performed between L1 and the key. The output of XOR unit and R1 are swapped using the swapper unit. Then, the outputs ofthe swapper unit is appendedusing bit append unit which produces 128-bits Ciphertext output. This ciphertext output is the desired encrypted data to be transmitted from the transmittertothereceiverthroughwire / wireless medium. 2.2 DECIPHERMENT ALGORITHM: The algorithm for the decryption process can be written in the reverse order of the encryption algorithm. 3. SIMULATION RESULT AND DISCUSSION The VHDL code of the proposed work has been simulated using Xilinx ISE 9.2i software and the desired results have been obtained. The simulation result of the encipherment process is given as follows: Fig 2: Simulation result of the encipherment process The simulation result of the decipherment process is given as follows: Fig 3: Simulation result of the decipherment process 4. CONCLUSION After doing the proposed work, it is concluded that the work is best suited in the field of data security to provide protection to the 128-bits original data from unauthorized access. It is resistant to the brute-force attack, timing attack, snooping attack, pattern attack, statistical attack which makes the algorithm more robust. The combinational path delay of the time required to convert 128-bits plaintext into 128-bits ciphertext is 8.063ns which obtained from the Xilinx software. REFERENCES [1] Dr. Sandeep Tayal, Dr. Nipin Gupta, Dr. Pankaj Gupta, Deepak Goyal, Monika Goyal, “A Review paper on Network Security and Cryptography”, Advances in Computational Sciences and Technology, Volume 10, Number 5,pp. 763- 770,2017. [2] J. G. Pandey,Aanchal Gurawa, Heena Nehra,A. Karmakar, “An efficient VLSI architecture for data encryption standard and itsFPGA implementation”,VLSI SATA,IEEEInternational Conference,pp.1-5,2016. [3] W.Stallings,“Cryptography and Network Security”, 2nd Edition, Prentice Hall. [4] Douglas L. Perry. “VHDL Programming by Examples”, TMH. [5] Soufiane Oukili,Seddik Bri,”FPGA implementationofData Encryption Standard using time variable permutations”, International Conference on Microelectronics (ICM),IEEE,pp.126-129,2015. [6] Ramadhan J. Mstafa; Khaled M. Elleithy, “A highly secure video steganography using Hamming code (7, 4)”, Systems, Applications and Technology Conference (LISAT), IEEE Conference,pp.1-6,2014. [7] Ravikumar M.Raypure, Prof. Vinay Keswani, “Implementation For Data Hiding Using Visual Cryptography”, IRJET, Volume: 04, Issue: 07, 2017.