![第18屆台灣靜電放電防護技術暨可靠度技術研討會
2019 Taiwan ESD and Reliability Conference
Only ‘local protection’ clamp is feasible: HBM simulations
21
• Transient simulation
– Voltage at input pad
during HBM stress
• Foundry solution &
dual diode approach
– Transient voltage
overshoot damages the
functional input circuit
• Local protection clamp
– Safe protection
6
4
2
Dual diode Sofics
Proposed local protection clamp
200 400 Time [ns]
Voltage
[V]
Foundry analog I/O
600 800
Failure
voltage](https://image.slidesharecdn.com/2019-11-07soficslowcapesdtaiwan-esd-200425090657/85/Local-I-O-ESD-protection-for-28Gbps-to-112Gbps-SerDes-interfaces-in-advanced-CMOS-and-FinFET-technology-21-320.jpg)
![第18屆台灣靜電放電防護技術暨可靠度技術研討會
2019 Taiwan ESD and Reliability Conference
Protection approach – 28nm Silicon Photonics
29
• ESD Capacitance
– Parasitic capacitance
▪ Junction
▪ Metal connections
– Across DC bias at input
• Rule of thumb
– Work vertically
– Remove vias where possible
– Reduce metal1 as much as
possible, keep it on top of
diffusion
▪ Closest to substrate!
▪ Do not cross junctions!
12fF
8fF
4fF
14.52fF total cap
8.6fF junction cap
0.2 0.8DC bias [V]
Capacitance
[fF]](https://image.slidesharecdn.com/2019-11-07soficslowcapesdtaiwan-esd-200425090657/85/Local-I-O-ESD-protection-for-28Gbps-to-112Gbps-SerDes-interfaces-in-advanced-CMOS-and-FinFET-technology-29-320.jpg)
Local I/O ESD protection for 28Gbps to 112Gbps SerDes interfaces in advanced CMOS and FinFET technology
- 1. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 1
- 2. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 2 Local I/O ESD protection for SerDes interfaces • Introduction • Traditional ESD approach for I/Os • Local ESD protection • SerDes case studies • Conclusions
- 3. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference High-speed SerDes interfaces need custom ESD 3 • SerDes interfaces cannot tolerate a lot of parasitics – No ESD-resistance allowed in the pad – Ultra-low parasitic capacitance required • SerDes interfaces need custom analog IOs – Operated at low voltage, below standard IO-levels • Advanced CMOS/FinFET technology – Very sensitive circuits need adequate protection – High speed circuit uses the thin oxide transistors
- 4. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Problem: advanced circuits easily fail during ESD 4 • Maximum voltage decreases – Transient breakdown of gate oxides – Burn-out of output drivers – Core failure voltage 28
- 5. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Problem: Traditional solutions not functional 5 • 16nm Core (0.8V) NMOS / PMOS – Does not survive snapback – Cannot be used as ESD clamp • 16nm IO (1.8V) NMOS/PMOS – Does not survive snapback – Junction failure at 4.5V – Cannot be used as ESD clamp – Cannot be made self-protective Core transistor failure below 4V
- 6. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Problem: Traditional solutions not good enough 6 • MOS BigFET clamp with enhanced trigger/hold circuit – MOS perimeter: 2800um – Area is still reasonable: 1800um² – Leakage is the bottle neck: ~0.5uA @ 0.8V @ 85°C • ESD performance of diodes further reduced – 35mA/um up to 65nm – 25mA/um in 40nm – 20mA/um in 28nm, 16nm – Diode perimeter scaling required ▪ To compensate for reduced performance ▪ But capacitive loading increases Circuit Vdd Vss IO
- 7. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 7 Local I/O ESD protection for SerDes interfaces • Introduction • Traditional ESD approach for I/Os • Local ESD protection • SerDes case studies • Conclusions
- 8. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Typical Analog I/O – diode based ESD approach 8 • Traditional Analog I/O – Simple concept ▪ Diode from Vss to Pad ▪ Diode from Pad to Vdd – Good characteristics ▪ Low leakage ▪ Low parasitic capacitance ▪ Small area – Needs efficient power/rail clamp ▪ Limited distance between I/O and rail clamp
- 9. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Dual diode: Influence of bus resistance 9 • Protection using diode up and power clamp – Voltage drop over diode, bus, Power clamp – Requirement: Total voltage drop below Vcritical Voltage Current GOX damage Vmin Vmax Design Window Normal operation ESD Spec. Vcritical Vdd Vss IN +
- 10. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Dual diode: Influence of bus resistance 10 Power Clamp Resistance of Vdd bus line Diode V I V I V I V I GOX damage Vmin Vmax ESD Spec. Effectiveness: NOT OK Vdd Vss IN + Robustness: OK
- 11. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Secondary Protection: Extending the design window • General idea: – Use isolation resistor to limit the current – (Small) Secondary clamp to limit voltage over gate oxide – Extend design window • Insert isolation resistor – Typical 50 – 100 Ohm 11 Voltage Current 1.0V Vhold Vt1 GOX damage 4V Vmax GAIN Normal operation Vdd Vss IN +
- 12. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Problems with traditional IO ESD concepts 12 • Traditional Analog I/O – Dual diode ▪ ESD level dependence on bus resistance ▪ Not effective for narrow design window – Secondary protection concept ▪ Better protection of sensitive nodes ▪ But resistance not tolerated for high speed circuits • Room for improvement – Effective protection without resistance – Overvoltage tolerant – Low parasitic capacitance
- 13. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 13 Local I/O ESD protection for SerDes interfaces • Introduction • Traditional ESD approach for I/Os • Local ESD protection • SerDes case studies • Conclusions
- 14. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Local protection concept – ESD clamp within the I/O 14 • Protection of high speed IOs based on core transistors – Self-protective devices not possible (does not survive snapback) – Dual Diode + railclamp not possible (ESD design window of 3V) • Solution: Local I/O clamp – Strongly reduce voltage drop during ESD ▪ Protect extremely sensitive nodes without Riso – Reduced dependence on bus resistance – Optimization possible for each interface – Allow higher ESD threshold – Allow reduced capacitance Vdd Vss IN +
- 15. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Local clamps used in this presentation 15 53.66um 11.59um ESD-ON-SCR 25.97um DTSCRESD-ON-SCR G2 A DTSCR G2 A
- 16. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 16 Local I/O ESD protection for SerDes interfaces • Introduction • Traditional ESD approach for I/Os • Local ESD protection • SerDes case studies – 16nm, 28 Gbps – Silicon photonics (28nm, 16nm, 7nm) • Conclusions
- 17. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 16nm FinFET: Local clamp, protecting core interface 17 • Protection of core interface – Extremely narrow ESD design window • Silicon verified solution – ESD-on-SCR – ESD: >2.1A TLP ▪ Area: <1000 um² – Leakage ▪ 1nA at 125°C
- 18. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Low parasitic capacitance – high speed interfaces 18 • Full local protection – ESD-on-SCR clamp – Protects 0.8V transistors • Frequency Sweep evaluation (AC sweep) – Evaluate phase-shift of input current to calculate capacitance – Step based input bias to evaluate offset influence – No metal effects yet! • Conclusion: – Suitable for 30Gbps interfaces
- 19. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Silicon Photonics – high speed optical communication 19 • Why optical links need custom ESD clamps? – Controlling ASIC is still an electrical IC – Based on advanced CMOS technology – ESD sensitive transistors need adequate protection • Several projects on various CMOS nodes – TSMC 180nm, 130nm, 40nm, 28nm – TSMC 16nm, 7nm FinFETS – SiGe BiCMOS process • Focus on CMOS ASIC (‘CPU’) – Protect high speed interconnects (Tx, Rx) – Protect low voltage, thin oxide domains
- 20. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 28nm Silicon Photonics application – Requirements 20 • ESD requirements – Regular, low speed IO circuits ▪ 1.8V, 2.5V or 3.3 – standard General Purpose IOs are used ▪ Standard requirements: 2kV HBM ▪ No focus for this work – Focus: 28 Gbps differential circuits ▪ 1V input/output using 0.9V thin oxide transistors ▪ No resistance in pad ▪ Ultra-low parasitic capacitance for ESD protection: maximum 20fF ▪ ESD-safe assembly: ESD Level reduced to 200V HBM (Human Body Model) ▪ ESD design window: shunt transient ESD current below 4V
- 21. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Only ‘local protection’ clamp is feasible: HBM simulations 21 • Transient simulation – Voltage at input pad during HBM stress • Foundry solution & dual diode approach – Transient voltage overshoot damages the functional input circuit • Local protection clamp – Safe protection 6 4 2 Dual diode Sofics Proposed local protection clamp 200 400 Time [ns] Voltage [V] Foundry analog I/O 600 800 Failure voltage
- 22. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference ESD Protection approach – 28nm Silicon Photonics 22 • ESD clamp design – Full local protection in both directions ▪ between IO and VSS, between IO and VDD – Integrated 1V power clamp ▪ For stress from VDD to VSS – Isolated from substrate to reduce noise interference – Small Area: ▪ 13.66um x 50.055um = 683.75 um² – Low Leakage current ▪ 10 pA at 25°C ▪ 10 nA at 125°C
- 23. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Capacitance Simulation 23 Junction Capacitance (based on models) Metal Capacitance (based on PEX) Total Input Capacitance
- 24. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 200V Clamp, 28nm process • Target <15fF • 1st round – All structures have their capacitance defined as ‘junction capacitance’ – Layout is based on bulk devices (all devices in substrate) – 1V I/O clamp, 200V HBM: 10.9fF junction cap... – Extraction and simulation returned a cap of > 100fF (including metal...) 24
- 25. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 200V Clamp, 28nm Process • 2nd round: quick modification – Remove metal lines and bring in signal vertically Cap Reduction: >100fF ➔ 33fF total Still 18fF too high... ➔ 25
- 26. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 200V Clamp, 28nm Process • 3rd round: metal rerouting – Redistribution of metal lines. Calculation of horizontal metals Cap Reduction: 33fF ➔ 19.4fF total Still 4.4fF too high... ➔ 26
- 27. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 200V Clamp, 28nm Process • 4th round: metal reduction – Number of vertical metals used decreased, removal of vias near I/O path Cap Reduction: 19.4fF ➔ 17.4fF total Still 2.4fF too high... ➔ 27
- 28. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 200V Clamp, 28nm Process • 5th round: metal reduction and junction reduction Relax design margins Cap Reduction: 17.4fF ➔ 16.07fF total Still 1.07fF too high... ➔ 28
- 29. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Protection approach – 28nm Silicon Photonics 29 • ESD Capacitance – Parasitic capacitance ▪ Junction ▪ Metal connections – Across DC bias at input • Rule of thumb – Work vertically – Remove vias where possible – Reduce metal1 as much as possible, keep it on top of diffusion ▪ Closest to substrate! ▪ Do not cross junctions! 12fF 8fF 4fF 14.52fF total cap 8.6fF junction cap 0.2 0.8DC bias [V] Capacitance [fF]
- 30. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: Sofics’ clamp – 28nm – Protection solution 30 • Protection of high speed pins – 1V input/output using 0.9V thin oxide transistors – Protection level ▪ 100V HBM – Area ▪ 13.66um x 15.875um = 216.9 um² ▪ Full local protection – Leakage current ▪ 10 pA at 25°C ▪ 10 nA at 125°C
- 31. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Case 2: Sofics’ clamp – 28nm – Parasitic capacitance 31 8fF 7.6fF SS-corner FF-corner 0.5 2DC bias (V) TT-corner
- 32. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 7nm low-cap. core interface protection 32 • Protection of core interface – Extremely narrow ESD design window • Silicon verified solution – SCR based solution • Different versions – 15fF parasitic capacitance ~ 250V HBM – 50fF parasitic capacitance ~ 700V HBM – 150fF parasitic capacitance ~ 2kV HBM
- 33. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Example: 7nm FinFET – low leakage I/O protection 33 • 0.75V core I/O protection clamp – Leakage ~ 10pA at room temperature – Leakage below 1nA at 125°C 125°C 25°C Operating range
- 34. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference 34 Local I/O ESD protection for SerDes interfaces • Introduction • Traditional ESD approach for I/Os • Local ESD protection • SerDes case studies • Conclusions
- 35. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Conclusions 35 • Problem: ‘dual diode’ ESD protection – Not suitable for ESD protection ▪ High speed SerDes ▪ Advanced CMOS and FinFET nodes. – Total voltage drop exceeds failure voltage. – Adds limitations • Local ESD protection clamps in the I/O pad – Proprietary Diode triggered and ESD-on-SCR devices. – Reduced dependence of the bus resistance – Reduced clamping voltage – Optimize every analog I/O separately. Vdd Vss IN + Vdd Vss IN +
- 36. 第18屆台灣靜電放電防護技術暨可靠度技術研討會 2019 Taiwan ESD and Reliability Conference Conclusions 36 • Presented case studies for local ESD protection – Low parasitic capacitance – Small silicon footprint – Low leakage • Based on dedicated ESD test chips – Advanced 28nm CMOS and 16nm, 7nm FinFET nodes. • Proven in products – Used by more than 20 companies – 10+ projects on Silicon photonics – Protection of high-speed SerDes interfaces up to 112Gbps