Logic Simulation, Modeling, and Testing
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The document discusses simulation, modeling, and testing in VLSI design. It covers various topics including logic simulation, fault simulation, and VLSI testing. Logic simulation verifies design correctness using simulation. Fault simulation measures test effectiveness by simulating faults. VLSI testing verifies manufactured chips using test generation and application. The document compares different simulation and testing techniques.
Logic Simulation, Modeling, and Testing
- 2. Outline Introduction Simulation Models Logic simulation Fault Simulation VLSI Testing References 12/22/2019 Simulation, Modeling, and Testing 2
- 3. Introduction Simulation: Refers to modeling of a design, its function and performance imitate the operation of a facility or process usually via a computer. used to: verify the correctness of the design verify the test to represent the system in software 12/22/2019 Simulation, Modeling, and Testing 3
- 4. Introduction… Simulation… Level of simulation: i. System level ii. Architecture level iii. Function level/RTL level iv.Gate/structural level v. Switch/transistor/circuit level vi.Mixed level 12/22/2019 Simulation, Modeling, and Testing 4
- 5. Introduction… Simulation process: 12/22/2019 Simulation, Modeling, and Testing 5 Library Simulator Stimuli Model Response Two types: a. Software simulator (i.e. a computer program). b. Hardware simulator known as an Emulator.
- 6. Introduction… Modeling: Formulating a system, studying a system for certain parameter to achieve. Simulation Models: Describing of modules, blocks, or components in terms of I/O functions and delays. Interconnects represent an ideal signal carriers or ideal electrical conductor. Netlist: a format (language) that describes a design as interconnection of modules 12/22/2019 Simulation, Modeling, and Testing 6
- 7. Introduction… Simulation Models… 12/22/2019 Simulation, Modeling, and Testing 7 Modeling level Circuit description Signal values Timing Application Function, Behavior, RTL Programming language like HDL 0,1 Clock boundary Architectural and functional verification Logic/Gate Connectivity of Boolean gates, flip- flops, and transistors 0, 1, x, and z Zero delay, unit delay, and multiple delay Logic verification and test Switch Transistor size and connectivity, node capacitance 0, 1, and x Zero delay Logic verification Timing Transistor technology data, connectivity, node capacitance Analog voltage Fine-grain timing Timing verification Circuit Tech. Data, active/ passive components, connectivity Analog voltage and current Continuous time Digital timing and analog
- 8. Logic simulation Also known as true-value simulation. It is the use of simulation software to predict the behavior of a digital circuit. Two types: i. Compiled simulation Simulate a digital system using high level programming language (e.g., system C). ii. Event-driven simulation Simulate a digital system when a signal changes 12/22/2019 Simulation, Modeling, and Testing 8
- 9. Logic simulation… i. Compiled simulation: Used for cycle-accurate synchronous sequential circuits for logic verification Applicable to zero-delay combination language Efficient for highly active circuits ii. Event-driven simulation: Perform gates or modules evaluation with input events. Delay can be accurately simulated for timing verification Efficient for low active circuits 12/22/2019 Simulation, Modeling, and Testing 9
- 10. Fault simulation Is simulating of a digital circuit in the presence of faults Its main goal is: Measuring the effectiveness of the test pattern Generating fault dictionaries Guiding the test pattern generator program Its output is: Fault coverage (i.e. fault detected by test vectors) Set of undetected fault 12/22/2019 Simulation, Modeling, and Testing 10
- 11. Fault simulation… Note: fault simulator affects the speed of the overall fault simulation. 12/22/2019 Simulation, Modeling, and Testing 11 Library Fault simulator Fault list Test set Evaluation Design model
- 12. Fault simulation… Four types of fault simulation algorithms: a. Serial fault simulation algorithm Fault free simulation + fault injection and simulation for each fault. b. Parallel fault simulation algorithm Uses a bit parallelism of logical operation c. Deductive fault simulation algorithm Deduce all signal values in each faulty circuit from simulated fault free circuit. d. Concurrent fault simulation algorithm All events of fault free and all faulty circuits are implicitly simulated 12/22/2019 Simulation, Modeling, and Testing 12
- 13. Fault simulation… a. Serial fault simulation algorithm: True-value simulation is performed across all vectors and outputs saved. Faulty circuits are simulated one-by-one by modifying circuit and running true-value simulator. Simulation of faulty circuit stops as soon as fault is detected. Advantage: Easy to implement Any type of fault can be simulated 12/22/2019 Simulation, Modeling, and Testing 13
- 14. Fault simulation… a. Serial fault simulation algorithm… Disadvantage: Many simulation runs required „CPU time prohibitive for VLSI circuits 12/22/2019 Simulation, Modeling, and Testing 14 Test vectors Fault free circuit Circuit with fault f1 Circuit with fault f2 Comparator Comparator Comparator Circuit with fault fn f1 detected f2 detected fn detected
- 15. Fault simulation… a. Serial fault simulation algorithm… Example: 12/22/2019 Simulation, Modeling, and Testing 15 Fault detected Fault undetected
- 16. Fault simulation… b. Parallel fault simulation algorithm: Assumption: The simulated circuit consists of only logic gates and all gates have the same delays „ Signals take only binary (0 and 1) values Taking advantage of inherent parallel operation of computer words to simulate faulty circuits in parallel with fault-free circuit Advantage: Straightforward and memory efficient 12/22/2019 Simulation, Modeling, and Testing 16
- 17. Fault simulation… b. Parallel fault simulation algorithm… Disadvantage: Lacking the capability to simulate accurate rise and fall delays of signals „ Not suitable for circuits with non-Boolean logic Example: Consider three faults: B/1, F/0, and J/0 12/22/2019 Simulation, Modeling, and Testing 17 J/0 B/1 F/0 FF Fault Free
- 18. Fault simulation… c. Deductive fault simulation algorithm: Only the fault free circuit is simulated Faulty circuit values are deduced from the fault-free values It processes all faults in a single pass of true-value simulation, i.e., it very fast! A vector is simulated in true-value mode. A deductive procedure is then performed on all lines in level-order from inputs to outputs Fault lists are generated for each signal using the fault lists on the inputs to the gate generating that signal 12/22/2019 Simulation, Modeling, and Testing 18
- 19. Fault simulation… c. Deductive fault simulation algorithm… Rules for fault list propagation: 12/22/2019 Simulation, Modeling, and Testing 19 Where: La and Lb indicates the error produced in line a and b respectively. C1 and C0 indicates an internal faults producing incorrect output
- 20. Fault simulation… c. Deductive fault simulation algorithm… Note: from probability concept, 12/22/2019 Simulation, Modeling, and Testing 20 Suppose: A = {1,2,3}, B = {3, 4, 5} A u B: all elements of A and B A n B: elements found in both A and B A/B: elements which is found in A not in B AΔ B: opposite of intersection A’: the elements which are not found in set A
- 21. Fault simulation… c. Deductive fault simulation algorithm… Example: 12/22/2019 Simulation, Modeling, and Testing 21
- 22. Fault simulation… d. Concurrent fault simulation algorithm: Event-driven simulation with fault-free and faulty circuits simulated altogether A list per gate containing copies of the gate from all faulty circuits in which this gate differs Event-driven simulation is carried out. Good-events and fault-events make good-gates active for evaluation. Good-events also make bad-gates active for evaluation Faster than other methods, but uses most memory 12/22/2019 Simulation, Modeling, and Testing 22
- 23. Fault simulation… d. Concurrent fault simulation algorithm… Example: 12/22/2019 Simulation, Modeling, and Testing 23
- 24. VLSI testing Verifies correctness of manufactured hardware Two-part process Test generation: software process executed once during design Test application: electrical tests applied to hardware Test application performed on every manufactured device Responsible for quality of device 12/22/2019 Simulation, Modeling, and Testing 24
- 25. VLSI testing… Test process: Fault modeling: what faults to test? Test pattern generation: how are test patterns obtained? fault simulation: how is test quality (fault coverage) measured? ATE/BIST: how are test vectors applied and result evaluated? Note: 12/22/2019 Simulation, Modeling, and Testing 25 A T E B I S T Automatic Test Equipment Built In Self Test
- 26. VLSI testing… Test process… 12/22/2019 Simulation, Modeling, and Testing 26
- 27. VLSI testing… Simulation for test: Deals with the behavior of fabricated circuit It determine the fault coverage of each input vector Used to: To determine test quality and in turn product quality To develop manufacturing test program 12/22/2019 Simulation, Modeling, and Testing 27 Fault coverage = Detected faults / Total no. of faults
- 28. VLSI testing… Logical fault model: Logical faults represent the effect of physical faults on the behavior of the system It may be: structural and functional structural faults are related to structural models functional faults are related to functional models Note: Why we model physical faults as logical ones? 12/22/2019 Simulation, Modeling, and Testing 28
- 29. VLSI testing… Logical fault model… A good fault model has two requirements: Accurately reflects the behavior of a physical defect Is computationally efficient with respect to simulation Current common fault models include: Gate level stuck-at faults Stuck-at-0 (sa0) & stuck-at-1 (sa1) Transistor level stuck faults Stuck-on (stuck-closed) & stuck-off (stuck-open) 12/22/2019 Simulation, Modeling, and Testing 29
- 30. VLSI testing… Logical fault model… Current common fault models include… Bridging faults (shorts between wires) Wired-AND & wired-OR Dominant (one driving source dominates the other) Note: opens in wires typically covered by stuck-faults Delay faults Excessive delay in a transition, a gate, or a path Known as transition, gate, or path delay fault, respectively 12/22/2019 Simulation, Modeling, and Testing 30
- 31. VLSI testing… Testing and Diagnosis: Testing is a process which includes test pattern generation, test pattern application, and output evaluation. Fault detection tells whether a circuit is fault-free or not Fault location provides the location of the detected faults Fault diagnosis provide the location and the type of the detected faults 12/22/2019 Simulation, Modeling, and Testing 31
- 32. VLSI testing… Algorithm types of test pattern generation: i. Exhaustive test generation Appropriate only when the number of PIs is small Detects all the combinational faults ii. Pseudo-exhaustive test generation Test most of universal faults by applying exhaustive test on subsets of PIs iii. Pseudo-random test generation a pseudo-random pattern generator is used to create a test patterns 12/22/2019 Simulation, Modeling, and Testing 32
- 33. Reference 1. Sherwood, W., 1981, June. A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge. In Proceedings of the 18th Design Automation Conference (pp. 775-785). IEEE Press. 2. Armstrong, D.B., 1972. A deductive method for simulating faults in logic circuits. IEEE Transactions on Computers, 100(5), pp.464-471. 3. Grout I., “An Analogue and Mixed-Signal Fault Simulation Tool based on Tcl/Tk and HSpice”, Proceedings of the Iberchip 2002 Workshop, Mexico, 2002 4. Lee, H.K. and Ha, D.S., 1996. HOPE: An efficient parallel fault simulator for synchronous sequential circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(9), pp.1048-1058. 5. Ju, Y.C., Yang, F.L. and Saleh, R.A., 1990, November. Mixed-mode incremental simulation and concurrent fault simulation. In 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (pp. 158-161). IEEE. 6. Balaji, G.N. and Pandian, S.C., 2019. Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates. Cluster Computing, 22(6), pp.15231-15244. 7. Lee, W.F. and Glaser, 2019. Learning from VLSI Design Experience. Springer International Publishing. 12/22/2019 Simulation, Modeling, and Testing 33