Logic synthesis using Verilog HDL

Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56
Logic synthesis with Verilog HDL
Mr. Anand H. D.
1
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology
Bengaluru-56

What is Logic synthesis? Impact of Logic Synthesis Verilog HDL synthesis
Synthesis Design Flow Verification of Gate Level Netlist
Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 2
SYLLABUS:
What is Logic synthesis?
Impact of Logic Synthesis
Verilog HDL synthesis
Synthesis Design Flow
Verification of Gate Level Netlist

What is Logic Synthesis?
logic synthesis is the process of converting a high-level description of the
design into an optimized gate-level representation, given a standard cell
library and certain design constraints.
A standard cell library can have simple cells, such as basic
logic gates like and, or, and nor, or macro cells, such as adders, muxes, and
special flipflops.
A standard cell library is also known as the technology library.
Logic synthesis always existed even in the days of schematic gate-level design,
but it was always done inside the designer's mind.

Designer's
Mind as the
Logic Synthesis
Tool
The designer would first understand the architectural
description. Then he would consider design
constraints such as timing, area, testability, and
power.
The designer would partition the design into high-
level blocks, draw them on a piece of paper or a
computer terminal, and describe the functionality of
the circuit. This was the high-level description.
Finally, each block would be implemented on a hand-
drawn schematic, using the cells available in the
standard cell library.
The last step was the most complex process in the
design flow and required several time-consuming
design iterations before an optimized gate-level
representation that met all design constraints was
obtained.
Thus, the designer's mind was used as the logic
synthesis tool, as illustrated in Figure.
Architectural
Description
Partition into High
level blocks
Designer’s Mind
Gate level
representation
Meets Design
constraints
Optimized Gate
level Representation
Design Constraints
Standard Cell
Library
(Technology
Dependent)
Designiterations
NO
YES

Meets
constraints
The advent of computer-aided logic synthesis tools has automated the
process of converting the high-level description to logic gates.
Instead of trying to perform logic synthesis in their minds, designers
can now concentrate on the architectural trade-offs,
high-level description of the design, accurate design constraints, and
optimization of cells in the standard cell library.
These are fed to the computer-aided logic synthesis tool, which
performs several iterations internally and generates the optimized
gate-level description.
Also, instead of drawing the high-level description on a screen or a
piece of paper, designers describe the high-level design in terms of
HDLs.
Verilog HDL has become one of the popular HDLs for the writing of
high-level descriptions. Figure illustrates the process
Automated logic synthesis has significantly reduced time for
conversion from high-level design representation to gates.
This has allowed designers to spend more time on designing at a
higher level of representation, because less time is required for
converting the design to gates
Basic Computer-
Aided Logic
Synthesis
Process
Architectural
Description
High level
Description
Computer Aided
Logic Synthesis
Optimized Gate
level netlist
Place and Route
Design Constraints
Standard Cell
Library
(Technology
Dependent)
NO
YES

What is Logic Synthesis? Impact of Logic Synthesis
Logic synthesis has revolutionized the digital design industry by significantly improving productivity and by
reducing design cycle time. Before the days of automated logic synthesis, when designs were converted to gates
manually, the design process had the following limitations:
• For large designs, manual conversion was prone to human error. A small gate missed somewhere could mean
redesign of entire blocks.
• The designer could never be sure that the design constraints were going to be met until the gate-level
implementation was completed and tested.
• A significant portion of the design cycle was dominated by the time taken to convert a high-level design into
gates.
• If the gate-level design did not meet requirements, the turnaround time for redesign of blocks was very high.
• What-if scenarios were hard to verify. For example, the designer designed a block in gates that could run at a
cycle time of 20 ns. If the designer wanted to find out whether the circuit could be optimized to run faster at 15
ns, the entire block had to be redesigned. Thus, redesign was needed to verify what-if scenarios.
• Each designer would implement design blocks differently. There was little consistency in design styles. For large
designs, this could mean that smaller blocks were optimized, but the overall design was not optimal.

• If a bug was found in the final, gate-level design, this would sometimes require redesign of thousands of gates.
• Timing, area, and power dissipation in library cells are fabrication-technology specific. Thus if the company
changed the IC fabrication vendor after the gate level design was complete, this would mean redesign of the
entire circuit and a possible change in design methodology.
• Design reuse was not possible. Designs were technology-specific, hard to port, and very difficult to reuse.
Automated logic synthesis tools addressed these problems as follows:
• High-level design is less prone to human error because designs are described at a higher level of abstraction.
• High-level design is done without significant concern about design constraints. Logic synthesis will convert a
high-level design to a gate-level netlist and ensure that all constraints have been met. If not, the designer goes
back, modifies the high-level design and repeats the process until a gate-level netlist that satisfies timing, area,
and power constraints is obtained.
• Conversion from high-level design to gates is fast. With this improvement, design cycle times are shortened
considerably. What took months before can now be done in hours or days.
• Turnaround time for redesign of blocks is shorter because changes are required only at the register-transfer
level; then, the design is simply resynthesized to obtain the gate-level netlist

• Logic synthesis tools optimize the design as a whole. This removes the problem with varied designer styles for
the different blocks in the design and suboptimal designs.
• If a bug is found in the gate-level design, the designer goes back and changes the high-level description to
eliminate the bug. Then, the high-level description is again read into the logic synthesis tool to automatically
generate a new gate-level description.
• Logic synthesis tools allow technology-independent design. A high-level description may be written without
the IC fabrication technology in mind. Logic synthesis tools convert the design to gates, using cells in the
standard cell library provided by an IC fabrication vendor. If the technology changes or the IC fabrication vendor
changes, designers simply use logic synthesis to retarget the design to gates, using the standard cell library for
the new technology.
• Design reuse is possible for technology-independent descriptions. For example, if the functionality of the I/O
block in a microprocessor does not change, the RTL description of the I/O block can be reused in the design of
derivative microprocessors. If the technology changes, the synthesis tool simply maps to the desired technology.

What is Logic Synthesis? Impact of Logic Synthesis Verilog HDL Synthesis
For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (RTL).
The term RTL is used for an HDL description style that utilizes a combination of data flow and behavioral
constructs.
Logic synthesis tools take the register transfer-level HDL description and convert it to an optimized gate-level
netlist.
Verilog and VHDL are the two most popular HDLs used to describe the functionality at the RTL level.
In this module, we discuss RTL-based logic synthesis with Verilog HDL.
Behavioral synthesis tools that convert a behavioral description into an RTL description are slowly evolving, but
RTL-based synthesis is currently the most popular design method.
Not all constructs can be used when writing a description for a logic synthesis tool.
In general, any construct that is used to define a cycle-by-cycle RTL description is acceptable to the logic
synthesis tool.
The capabilities of individual logic synthesis tools may vary.
Verilog Constructs

The constructs that are typically acceptable to logic synthesis tools are also shown.
Construct Type Keyword or Description Notes
ports input, inout, output
parameters parameter
module
definition
module
signals and
variables
wire, reg, tri Vectors are allowed
instantiation
module instances,
primitive gate instances
E.g., mymux m1(out, i0, i1, s); E.g., nand
(out, a, b);
functions and
tasks
function, task Timing constructs ignored
procedural
always, if, then, else, case,
casex, casez
initial is not supported
procedural
blocks
begin, end, named blocks,
disable
Disabling of named blocks allowed
data flow assign Delay information is ignored
loops for, while, forever,
while and forever loops must contain
@(posedge clk) or @(negedge clk)

Remember that we are providing a cycle-by-cycle RTL description of the circuit. Hence, there are restrictions
on the way these constructs are used for the logic synthesis tool.
For example, the while and forever loops must be broken by a @ (posedge clock) or @ (negedge clock)
statement to enforce cycle-by-cycle behavior and to prevent combinational feedback.
Another restriction is that logic synthesis ignores all timing delays specified by #<delay> construct. Therefore,
pre- and post-synthesis Verilog simulation results may not match. The designer must use a description style that
eliminates these mismatches.
Also, the initial construct is not supported by logic synthesis tools. Instead, the designer must use a reset
mechanism to initialize the signals in the circuit.
It is recommended that all signal widths and variable widths be explicitly specified.
Defining unsized variables can result in large, gate-level netlists because synthesis tools can infer unnecessary
logic based on the variable definition
Almost all operators in Verilog are allowed for logic synthesis. T
Only operators such as === and !== that are related to x and z are not allowed, because equality with x and z
does not have much meaning in logic synthesis.
While writing expressions, it is recommended that you use parentheses to group logic the way you want it to
appear.
If you rely on operator precedence, logic synthesis tools might produce an undesirable logic structure.
Verilog Operators

Having described the basic Verilog constructs, let us try to understand how logic synthesis tools frequently
interpret these constructs and translate them to logic gates.
The assign construct is the most fundamental construct used to describe combinational logic at an RTL level.
Given below is a logic expression that uses the assign statement.
assign out = (a & b) | c;
This will frequently translate to the following gate-level representation:
Interpretation of a Few Verilog Constructs
If a, b, c, and out are 2-bit vectors [1:0], then the above assign statement will frequently translate to two
identical circuits for each bit.
The assign statement

If arithmetic operators are used, each arithmetic operator is implemented in terms of arithmetic hardware
blocks available to the logic synthesis tool. A 1-bit full adder is implemented below.
assign {c_out, sum} = a + b + c_in;
Assuming that the 1-bit full adder is available internally in the logic synthesis tool, the above assign statement
is often interpreted by logic synthesis tools as follows:
If a multiple-bit adder is synthesized, the synthesis tool will perform optimization and the designer might get a
result that looks different from the above figure.

If a conditional operator ? is used, a multiplexer circuit is inferred.
assign out = (s) ? i1 : i0;
It frequently translates to the gate-level representation shown in below Figure
The if-else statement
Single if-else statements translate to multiplexers where the control signal is the signal or variable in the if clause.
if(s) out = i1;
else out = i0;
The above statement will frequently translate to the gate-level description shown in above Figure only.
In general, multiple if-else-if statements do not synthesize to large multiplexers.

The case statement
The case statement also can used to infer multiplexers. The multiplexer would have been inferred from the
following description that uses case statements:
case (s)
1'b0 : out = i0;
1'b1 : out = i1;
endcase
Large case statements may be used to infer large multiplexers.
for loops
The for loops can be used to build cascaded combinational logic. For example, the following for loop builds an
8-bit full adder:
c = c_in;
for(i=0; i <=7; i = i + 1)
{c, sum[i]} = a[i] + b[i] + c; // builds an 8-bit ripple adder
c_out = c;
The always statement
The always statement can be used to infer sequential and combinational logic. For
sequential logic, the always statement must be controlled by the change in the value of a clock signal clk.
always @(posedge clk)
q <= d;
This is inferred as a positive edge-triggered D-flipflop with d as input, q as output, and clk as the clocking signal

Similarly, the following Verilog description creates a level-sensitive latch:
always @(clk or d)
if (clk)
q <= d;
For combinational logic, the always statement must be triggered by a signal other than the clk, reset, or preset.
For example, the following block will be interpreted as a 1-bit full adder:
always @(a or b or c_in)
{c_out, sum} = a + b + c_in;
The function statement
Functions synthesize to combinational blocks with one output variable. The output might be scalar or vector.
A 4-bit full adder is implemented as a function in the Verilog description below. The most significant bit of the
function is used for the carry bit.
function [4:0] fulladd;
input [3:0] a, b;
input c_in;
begin
fulladd = a + b + c_in; //bit 4 of fulladd for carry, bits[3:0] for sum.
end
endfunction

Verilog constructs are interpreted by the logic synthesis tool
Let us now discuss the synthesis design flow from an RTL
description to an optimized gate-level description.
RTL to Gates
To fully utilize the benefits of logic synthesis, the designer
must first understand the flow from the high-level RTL
description to a gate-level netlist.
Figure that flow.
RTL description
The designer describes the design at a high level by
using RTL constructs.
The designer spends time in functional verification to
ensure that the RTL description functions correctly.
After the functionality is verified, the RTL description
is input to the logic synthesis tool.
RTL Description
Translation
Unoptimized Intermediate
Representation
Logic Optimization
Optimized Gate Level Representation
Technology
Mapping &
Optimization
Logic Synthesis Flow from RTL to Gates
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)

The RTL description is converted by the logic synthesis tool to
an unoptimized, intermediate, internal representation. This
process is called translation.
Translation is relatively simple and uses Interpretation of a
Few Verilog Constructs.
The translator understands the basic primitives and operators
in the Verilog RTL description.
Design constraints such as area, timing, and power are not
considered in the translation process.
At this point, the logic synthesis tool does a simple allocation
of internal resources. .
RTL Description
Translation
Representation
Logic Optimization
Technology
Mapping &
Optimization
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)
The translation process yields an unoptimized
intermediate representation of the design.

The design is represented internally by the logic
synthesis tool in terms of internal data structures.
The unoptimized intermediate representation is in
comprehensible to the user.
Translation
Unoptimized intermediate representation

The logic is now optimized to remove redundant logic. Various
technology independent boolean logic optimization techniques are
used. This process is called logic optimization.
It is a very important step in logic synthesis, and it yields an
optimized internal representation of the design.
RTL Description
Translation
Representation
Logic Optimization
Technology
Mapping &
Optimization
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)
Until this step, the design description is independent of a specific
target technology.
In this step, the synthesis tool takes the internal representation and
implements the representation in gates, using the cells provided in the
technology library.
In other words, the design is mapped to the desired target technology.
Suppose you want to get your IC chip fabricated at ABC Inc.
ABC Inc. has 0.65 micron, CMOS technology, which it calls
abc_100 technology. Then, abc_100 becomes the target
technology. You must therefore implement your internal design
representation in gates, using the cells provided in abc_100 technology
library. This is called technology mapping.
Also, the implementation should satisfy such design constraints as
timing, area, and power. Some local optimizations are done to achieve
the best results for the target technology. This is called technology
optimization or technology-dependent optimization
Logic optimization
Technology mapping and optimization

The technology library contains library cells provided by ABC Inc.
To build a technology library, ABC Inc. decides the range of functionality
to provide in its library cells.
Library cells can be basic logic gates or macro cells such as adders,
ALUs, multiplexers, and special flip-flops.
The library cells are the basic building blocks that ABC Inc. will use for
IC fabrication. Physical layout of library cells is done first. Then, the area
of each cell is computed from the cell layout.
Next, modeling techniques are used to estimate the timing and power
characteristics of each library cell. This process is called cell
characterization.
Finally, each cell is described in a format that is understood by the
synthesis tool. The cell description contains information about
the following: •Functionality of the cell
•Area of the cell layout
•Timing information about the cell
•Power information about the cell
A collection of these cells is called the technology library.
The synthesis tool uses these cells to implement the design. The quality
of results from synthesis tools will typically be dominated by the cells
available in the technology library.
If the choice of cells in the technology library is limited, synthesis tool
cannot do much in terms of optimization for timing, area, and power
RTL Description
Translation
Representation
Logic Optimization
Technology
Mapping &
Optimization
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)
Technology library

Design constraints typically include the following:
• Timing? The circuit must meet certain timing requirements. An
internal static timing analyzer checks timing
• Area? The area of the final layout must not exceed a limit.
• Power? The power dissipation in the circuit must not exceed a
threshold.
In general, there is an inverse relationship between area and timing
constraints. For a given technology library, to optimize timing (faster
circuits), the design has to be parallelized, which typically means that
larger circuits have to be built. To build smaller circuits, designers must
generally compromise on circuit speed.
RTL Description
Translation
Representation
Logic Optimization
Technology
Mapping &
Optimization
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)
Design constraints
On top of design constraints, operating environment factors, such as
input and output delays, drive strengths, and loads, will affect the
optimization for the target technology.
Operating environment factors must be input to the logic synthesis
tool to ensure that circuits are optimized for the required operating
environment.
Area vs. Timing Trade-off

After the technology mapping is complete, an optimized
gate-level netlist described in terms of target technology
components is produced.
If this netlist meets the required constraints, it is handed to
ABC Inc. for final layout. Otherwise, the designer modifies the
RTL or reconstrains the design to achieve the desired results.
This process is iterated until the netlist meets the required
constraints.
ABC Inc. will do the layout, do timing checks to ensure that
the circuit meets required timing after layout,
and then fabricate the IC chip for you.
RTL Description
Translation
Representation
Logic Optimization
Technology
Mapping &
Optimization
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)
Optimized gate-level description

RTL Description
Translation
Representation
Logic Optimization
Technology
Mapping &
Optimization
Design
Constraints
Library of
available gates
and leaf level
cells(technology
library)
There are three points to note about the synthesis flow.
1. For very high speed circuits like microprocessors, vendor technology
libraries may yield nonoptimal results. Instead, design groups obtain
information about the fabrication process used by the vendor, for
example, 0.65 micron CMOS process, and build their own technology
library components. Cell characterization is done by the designers.
2. Translation, logic optimization, and technology mapping are done
internally in the logic synthesis tool and are not visible to the designer.
The technology library is given to the designer. Once the technology is
chosen, the designer can control only the input RTL description and
design constraint specification.
Thus, writing efficient RTL descriptions, specifying design
constraints accurately, evaluating design trade-offs, and having a good
technology library are very important to produce optimal digital
circuits when using logic synthesis.
3. For submicron designs, interconnect delays are becoming a
dominating factor in the overall delay.
Therefore, as geometries shrink, in order to accurately model
interconnect delays, synthesis tools will need to have a tighter link to
layout, right at the RTL level. Timing analyzers built into synthesis tools
will have to account for interconnect delays in the total delay
calculation.

An Example of RTL-to-Gates.
Let us discuss synthesis of a 4-bit magnitude comparator to understand each step in the synthesis flow.
Steps of the synthesis flow such as translation, logic optimization, and technology mapping are not visible to
us as designers.
Therefore, we will concentrate on the components that are visible to the designer, such as the RTL
description, technology library, design constraints, and the final, optimized, gate-level description.
A magnitude comparator checks if one number is greater than, equal to, or less than another number.
Design a 4-bit magnitude comparator IC chip that has the following
specifications:
• The name of the design is magnitude_comparator
• Inputs A and B are 4-bit inputs. No x or z values will appear on A and B inputs
• Output A_gt_B is true if A is greater than B
• Output A_lt_B is true if A is less than B
• Output A_eq_B is true if A is equal to B
• The magnitude comparator circuit must be as fast as possible. Area can be compromised for speed.
Design specification

The RTL description that describes the
magnitude comparator is shown in following
Example.
This is a technology-independent
description. The designer does not have to
worry about the target technology at this
point.
RTL description RTL for Magnitude Comparator
//Module magnitude comparator
module magnitude_comparator(A_gt_B, A_lt_B, A_eq_B, A, B);
//Comparison output
output A_gt_B, A_lt_B, A_eq_B;
//4-bits numbers input
input [3:0] A, B;
assign A_gt_B = (A > B); //A greater than B
assign A_lt_B = (A < B); //A less than B
assign A_eq_B = (A == B); //A equal to B
endmodule
//Library cells for abc_100 technology
VNAND//2-input nand gate
VAND//2-input and gate
VNOR//2-input nor gate
VOR//2-input or gate
VNOT//not gate
VBUF//buffer
NDFF//Negative edge triggered D flip-flop
PDFF//Positive edge triggered D flip-flop
We decide to use the 0.65 micron CMOS process
called abc_100 used by ABC Inc. to make our IC
chip. ABC Inc. supplies a technology library for
synthesis.
The library contains the following library cells. The
library cells are defined in a format understood by
the synthesis tool.
Functionality, timing, area, and power dissipation
information of each library cell are specified in the
technology library
Technology library

According to the specification, the design should be as fast as
possible for the target technology, abc_100. There are no area
constraints. Thus, there is only one design constraint.
• Optimize the final circuit for fastest timing
Design constraints
The RTL description of the magnitude comparator is read by the
logic synthesis tool.
The design constraints and technology library for abc_100 are
provided to the logic synthesis tool.
The logic synthesis tool performs the necessary optimizations
and produces a gate level description optimized for abc_100
technology.
Logic synthesis
The logic synthesis tool produces a final, gate-level description.
The schematic for the gate-level circuit is shown in Figure.
Final, Optimized, Gate-Level Description

Gate-Level Description for the Magnitude Comparator
module magnitude_comparator ( A_gt_B, A_lt_B, A_eq_B, A, B );
input [3:0] A;
input [3:0] B;
output A_gt_B, A_lt_B, A_eq_B;
wire n60, n61, n62, n50, n63, n51, n64, n52, n65, n40, n53, n41, n54, n42, n55, n43, 56, n44, n57, n45, n58,
n46, n59, n47, n48, n49, n38, n39;
VAND U7 ( .in0(n48), .in1(n49), .out(n38) );
VNOT U30 ( .in(A[2]), .out(n62) );
VNOT U31 ( .in(A[1]), .out(n59) );
VNOT U32 ( .in(A[0]), .out(n60) );
VNAND U20 ( .in0(B[2]), .in1(n62), .out(n45) );
VNAND U21 ( .in0(n61), .in1(n45), .out(n63) );
VOR U23 ( .in0(n60), .in1(B[0]), .out(n57) );
VOR U13 ( .in0(n58), .in1(B[3]), .out(n42) );
VOR U26 ( .in0(n62), .in1(B[2]), .out(n46) );
The gate-level Verilog description produced by the logic synthesis tool for the circuit is shown below. Ports are connected by name.
VOR U16 ( .in0(n59), .in1(B[1]), .out(n52) );
VNOT U29 ( .in(A[3]), .out(n58) );
VAND U2 ( .in0(n38), .in1(n39), .out(A_eq_B) );
VNAND U3 ( .in0(n40), .in1(n41), .out(A_lt_B) );
VNAND U4 ( .in0(n42), .in1(n43), .out(A_gt_B) );
endmodule
IC Fabrication
The gate-level netlist is verified for functionality and timing and then submitted to ABC Inc. ABC Inc. does the chip layout, checks that the post-layout
circuit meets timing requirements, and then fabricates the IC chip, using abc_100 technology

Multiprocessing and Multitasking
Synthesis Design Flow Verification of Gate level Netlist
The optimized gate-level netlist produced by the logic synthesis tool must be verified for functionality.
Also, the synthesis tool may not always be able to meet both timing and area requirements if they are too
stringent. Thus, a separate timing verification can be done on the gate-level netlist.
Functional Verification
Identical stimulus is run with the original RTL and synthesized gate-level descriptions of the design. The output is
compared to find any mismatches. For the magnitude comparator, a sample stimulus file is shown below.
Example: Stimulus for Magnitude Comparator
module stimulus;
reg [3:0] A, B;
wire A_GT_B, A_LT_B, A_EQ_B;
magnitude_comparator MC(A_GT_B, A_LT_B, A_EQ_B, A, B);
//Instantiate the magnitude comparator
initial
$monitor($time," A = %b, B = %b, A_GT_B = %b, A_LT_B =
%b, A_EQ_B = %b", A, B, A_GT_B, A_LT_B, A_EQ_B);
initial
begin
A = 4'b1010; B = 4'b1001;
# 10 A = 4'b1110; B = 4'b1111;
# 10 A = 4'b0000; B = 4'b0000;
# 10 A = 4'b1000; B = 4'b1100;
# 10 A = 4'b0110; B = 4'b1110;
# 10 A = 4'b1110; B = 4'b1110;
end
endmodule

The same stimulus is applied to both the RTL description and the synthesized gate-level description and the
simulation output is compared for mismatches.
However, there is an additional consideration. The gate-level description is in terms of library cells VAND, VNAND,
etc. Verilog simulators do not understand the meaning of these cells.
Thus, to simulate the gate-level description, a simulation library, abc_100.v, must be provided by ABC Inc. The
simulation library must describe cells VAND, VNAND, etc., in terms of Verilog HDL primitives and, nand, etc.
For example, the VAND cell will be defined in the simulation library as shown below
Example: Simulation Library //Simulation Library abc_100.v. Extremely simple. No timing checks.
module VAND (out, in0, in1);
input in0;
input in1;
output out;
//timing information, rise/fall and min:typ:max
Specify (in0 => out) = (0.260604:0.513000:0.955206, 0.255524:0.503000:0.936586);
(in1 => out) = (0.260604:0.513000:0.955206, 0.255524:0.503000:0.936586);
endspecify
//instantiate a Verilog HDL primitive
and (out, in0, in1);
endmodule
…
//All library cells will have corresponding module definitions
//in terms of Verilog primitives. Stimulus is applied to the RTL
description and the gate-level description. A typical invocation with a
Verilog simulator is shown below.

The simulation output must be identical for the two simulations. In our case, the output is identical. For the example
of the magnitude comparator, the output is shown below
Output from Simulation of Magnitude Comparator
0 A = 1010, B = 1001, A_GT_B = 1, A_LT_B = 0, A_EQ_B = 0
10 A = 1110, B = 1111, A_GT_B = 0, A_LT_B = 1, A_EQ_B = 0
20 A = 0000, B = 0000, A_GT_B = 0, A_LT_B = 0, A_EQ_B = 1
30 A = 1000, B = 1100, A_GT_B = 0, A_LT_B = 1, A_EQ_B = 0
40 A = 0110, B = 1110, A_GT_B = 0, A_LT_B = 1, A_EQ_B = 0
50 A = 1110, B = 1110, A_GT_B = 0, A_LT_B = 0, A_EQ_B = 1
//Apply stimulus to RTL description
> verilog stimulus.v mag_compare.v
//Apply stimulus to gate-level description.
//Include simulation library "abc_100.v" using the -v option
> verilog stimulus.v mag_compare.gv -v abc_100.v
Stimulus is applied to the RTL description and the gate-level description. A typical invocation with a Verilog simulator
is shown below

Timing verification
The gate-level netlist is typically checked for timing by use of timing simulation or by a static timing verifier.
If any timing constraints are violated, the designer must either redesign part of the RTL or make trade-offs in design
constraints for logic synthesis.
The entire flow is iterated until timing requirements are met
If the output is not identical, the designer needs to check for any potential bugs and rerun the whole flow until all
bugs are eliminated.
Comparing simulation output of an RTL and a gate-level netlist is only a part of the functional verification process.
Various techniques are used to ensure that the gate-level netlist produced by logic synthesis is functionally correct.
One technique is to write a high-level architectural description in C++. The output obtained by executing the highlevel
architectural description is compared against the simulation output of the RTL or the gate-level description.
Another technique called equivalence checking is also frequently used.

Reference
Samir Palnitkar, “Verilog HDL-A Guide to
Digital Design and Synthesis”, Pearson, 2003

Prepared by Prof. Anand H D,Dept. of ECE,
Dr. AIT, Bengaluru-56
33

Logic synthesis using Verilog HDL

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