Memory interfacing of microprocessor 8085

Memory Interfacing with Microprocessor 8085
Dr. Nilesh Bhaskarrao Bahadure
https://www.sites.google.com/site/nileshbbahadure/home
July 26, 2021
Dr. Nilesh Bhaskarrao Bahadure () Unit - IV (Part I) July 26, 2021 1 / 59

Overview I
1 Semiconductor Memory Fundamentals
2 Memory Types
3 Memory Structure and its requirements
4 Memory Decoding
Comparison of Full and Partial Decoding
5 Examples
Example - 1: 8KB EPROM and 8KB RAM
Example - 2: 16KB EPROM and 4KB RAM using 8KB EPROM and
2KB RAM
Example - 3: 2KB RAM using IC 2114
Example - 4: 2KB EPROM and 2KB RAM with give address
Example - 5: 4KB EPROM and 2KB RAM using 2KB EPROM and
1KB RAM
Example - 6: 8KB EPROM and 8 KB RAM using Linear Addressing
Wait state generator

Overview II
Example - 7: 8KB EPROM and 8 KB RAM with one wait state in
each machine cycle
read machine cycle
read & write machine cycle
6 Input - Output Interfacing
Input Port
Output Port
I/O Interfacing Techniques
I/O Mapped I/O
I/O Device Selection
Example - 1: Interfacing Input Switches
Example - 2: Interfacing LED’s (Output Device)
Example - 3: Interfacing Switches & LED’s
Memory mapped I/O

Overview III
Comparison Between Memory Mapped I/O and I/O Mapped I/O
7 Types of Parallel Data Transfer or I/O Techniques
Synchronous parallel data transfer
Asynchronous parallel data transfer
Asynchronous parallel data transfer using status signal or polling or
programmed control input/output
Asynchronous parallel data transfer using Ready pin or WAIT state
Asynchronous parallel data transfer using interrupt or interrupt control
input/output
Asynchronous parallel data transfer using handshake signals
Asynchronous data transfer using DMA (Direct memory access) operation.
8 Thank You

Memory is simply a device that can be used to store the information (data).
The semiconductor memories are extensively used because of their small size,
low cost, high speed, high reliability and ease of expansion of the memory
size, it consists mainly a flip flops one flip flop can hold one bit of data and
some additional circuitry such as buffers

Semiconductor Memory
1 In the design of all computers, semiconductor memories are used as
primary storage for data and code.
2 They are connected directly to the CPU and they are the memory
that the CPU asks for information (code or data).
3 Among the most widely used are RAM and ROM.
Memory Capacity
4 The number of bits that a semiconductor memory chip can store is
called its chip Capacity (bits or bytes)
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Semiconductor Memory
Memory Organization
1 Each memory chip contains 2N locations where N is the number of
address pins on the chip.
2 Each location contains M bits, where M is the number of data pins on
the chip.
3 The entire chip will contain 2N x M bits.
4 Example: Memory organization of 4K x 4, 212 = 4096 locations, each
location holding 4 Bits (so N=12 and M=4)
5 Memory Speed (access time)
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ROM I

ROM II
1 ROM (Read Only Memory)
ROM is the type of memory that does not lose its contents when
power is turned off. It is also called nonvolatile memory.
2 PROM (Programmable Memory)
User programmable (one-time programmable) memory.
If the information burned into PROM is wrong, it needs to be
discarded since internal fuses are blown permanently.
Special equipment needed: ROM burner or ROM programmer.
3 EPROM (Erasable Programmable ROM) 2,000 times
Allows making changes in the contents of PROM after it is burned.
One can program the memory chip and erase it thousands of times.
Erasing its contents can take up to 20 minutes; the entire chip is
erased.

ROM III
All EPROM chips have a window that is used to shine ultraviolet (UV)
radiation to erase its contents.
Also referred to as UV-EPROM.
4 EEPROM (Electrically Erasable ROM) 500,000 times
Method of erasure is electrical.
Moreover, one can select which byte to be erased.
Cost per bit is much higher than for UV-EPROM.
5 Flash Memory EPROM
First, the process of erasure of the entire contents takes less than a
second, or one might say in a flash, hence its name: flash memory.
When flash memorys contents are erased, the entire device is erased.
Even though flash memories are writeable, like EPROMs they find their
widest use in microcomputer systems for storage of firmware.
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Random Access Memory I

Random Access Memory II
1 SRAM (Static RAM)
Storage cells are made of flip-flops and therefore they do not require
refreshing to keep their data.
A cell handling one bit requires 6 or 4 transistors each, which is too
many.
SRAMS are widely used for cache memory and battery-backed memory
systems.
2 DRAM (Dynamic RAM)
Uses MOS capacitors to store a bit
Requires constant refreshing due to leakage (every 2ms 4ms).

Random Access Memory III
Advantages
a. High density (capacity),
b. Cheaper cost per bit
c. Lower power consumption.
Disadvantage
a. While it is being refreshed, data cannot be accessed
b. Larger access times
c. Too many pins due to large capacity
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Memory Device
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Memory structure of RAM and ROM
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Basic Concept of Memory Interfacing
The memory interfacing requires:
Select the chip (Enable CS).
Identify the register.
Enable the appropriate buffer ( Read or Write)
Microcontroller based system include memory devices and the input output
devices. It is important to note that microprocessor can communicate (Read
or Write) with only one device at a time, since the address, data and control
lines are common for all the devices.
In order to communicate with memory or IO device, it is necessary to decode
the address from the microprocessor.
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Absolute or Full Decoding

Partial or Linear Decoding
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Comparison of Full and Partial Decoding
Full Address Decoding Partial Address Decoding
All higher address lines are decoded
to select the memory or IO device
Few higher address lines are decoded
to select the memory or IO device
More hardware is required to design
decoding logic
Hardware required to design decoding
logic is less and sometimes it can be
eliminated
Higher cost for decoding circuit Less cost for decoding circuit
No multiple addresses It has a disadvantage of multiple ad-
dresses (shadow address)
Used in large system used in small system
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Example - 1
Show the interfacing of 8KB EPROM and 8 KB RAM with Microprocessor
8085.
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Example - 2
Design a Microprocessor 8085 based system such that it has 16 KB of
EPROM and 4 KB of RAM using two 8 KB EPROM (2764) and two 2 KB
RAM (6116).
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Example - 3
Interface 2KB RAM with Microprocessor 8085 using 2114 (1K x 4)
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Example - 4
Design a Microprocessor 8085 based system such that it has 2 KB of
EPROM and 2 KB of RAM with starting addresses 0000h and 6000h
respectively.
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Example - 5
Design a Microprocessor 8085 based system such that it should contain 4
KB of EPROM and 2 KB of RAM using two 2 KB of EPROMs and two 1
KB of RAM
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Example - 6
KB of EPROM and 8 KB of RAM. Use linear address decoding technique.
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Wait state generator
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Example - 7
KB of EPROM and 8 KB of RAM with one wait state in each machine
cycle.
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Example - 8
KB of EPROM and 8 KB of RAM with one wait state memory read
machine cycle only.
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Example - 9
KB of EPROM and 8 KB of RAM with one wait state memory read and
memory write machine cycle.
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Input - Output Interfacing

Introduction
Any application of a microprocessor based system requires the transfer of
data between external circuitry to the microprocessor and microprocessor
to the external circuitry. User can give information to the microprocessor
using keyboard and can see the result or output information from the mi-
croprocessor to the display devices. This exchange of information can be
done with the help of I/O ports.
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Input Port
Whenever the data is being read from the input device (say keyboard) by
the microprocessor after assertion of the enable input of the buffer, the data
from the input device will be available on the data bus. Thus a tri - state
buffer will be used for the input port.
Figure : Input port device (Tristate Buffer)
However, the input data byte will be obtained by enabling a tri - state buffer

Output Port
Whenever the microprocessor wants to send data to the output device, the
data is being kept on the data bus. When LE signal is enabled, the data is
being latched from the data bus at the output of the latch. It will be then
available for the output device for display through blinking of LED or any
other means.
Figure : Output port device (Latch)
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Example
Explain why a latch is used for an output port, but a tri - state buffer can
be used for an input port.
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I/O Interfacing Techniques
The most of the microprocessor supported isolated I/O system. It partitions
memory from IO via software, by having instructions that specifically access
memory, and other that specifically access IO. In 8085, IO/M signal is used
for this purpose.
I/O devices can be interfaced to an 8085 system in two ways:
1. I/O Mapped I/O
2. Memory Mapped I/O
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I/O Mapped I/O
In I/O mapped I/O, the 8085 uses IO/M signal to distinguish between
I/O read/write and memory read/write operations. The 8085 has sepa-
rate instructions IN and OUT for I/O data transfer. When 8085 executes
IN or OUT instruction, it places device address (port number) on the de-
multiplexed low order address bus as well as on the high order address bus.
For example, if the device address is 60h then the contents on A15 to A0
will be as follows
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0
Here, A8 follows A0, A9 follows A1 and so on, as shown below
A15 A14 A13 A12 A11 A10 A9 A8
Device Address
A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 0 0 0 0 0 60h
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I/O Device Selection
(a) Generation of a device address: The address bus is first de-
coded so as to generate a unique pulse in correspondent to the device ad-
dress on the bus called I/O address pulse or the device address pulse.
(b) Selection pulse for the device: The device address pulse gen-
erated is ANDed with the control signal in order to produce a device select
pulse. This pulse will be generated only when both the signals are activated.
(c) Activation of an I/O port: The I/O port select pulse is used to
activate the interfacing device (I/O Port)
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Example - 1: Interfacing Input Switches
Show the interfacing of 8 DIP switches using the port address 64h, also
write an assembly language program to check switch 2 is pressed or not.
Main Slide

Solution
Hardware Arrangement:
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Assembly Language Program
IN 64h ; Read status of all switches
ANI 02h ; Mask bit positions for other switches
JZ NEXT ; go to label next if switch 2 is pressed
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Example - 2: Interfacing LED’s (Output Device)
Show the interfacing of 8 LED’s (Common Anode) using the port address
6Ch, also write an assembly language program to on lower nibble of LED’s
only
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Solution
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MVI A, F0h ; Pattern for OFF higher nibble and ON lower nibble
OUT 6Ch ; sends data on the latch
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Example - 3: Interfacing Switches & LED’s
Show the interfacing of 8 Switches and 8 LED’s (Common Anode) with
Microprocessor 8085. Assume the port address for the latch is F8h and for
the buffer is FBh. Write an assembly language program that will check the
switch 1 and do the following accordingly
(a) SW1 = 0 Blink lower nibble LED’s
(b) SW1 = 1 Blink higher nibble LED’s
Assume suitable delay
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Solution
Main Slide

LXI SP, 27FFh ;Initialize stack pointer
START: IN FBh ;Read status of switches
ANI 01h ;Mask bit 1 to bit 7
JNZ HIGHER ;if SW1 = 1 go to blink higher nibble
MVI A, F0h ;Load bit pattern for glow lower nibble LED
OUT F8h ;Send it to output port
CALL DELAY ;Delay
MVI A, FFh
OUT F8h
CALL DELAY
JMP START
HIGHER: MVI A, 0Fh
OUT F8H
CALL DELAY
MVI A, FFh
OUT F8h
CALL DELAY
JMP START
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Memory mapped I/O
In memory mapped I/O, the I/O devices are assigned and identified by 16
- bit addresses. The memory related instructions transfer the data between
an I/O device and the Microprocessor, as long as I/O port is assigned to the
memory address space rather than to the I/O address space. The register
associated with the I/O port is simply treated as memory location. Thus
I/O device becomes a part of the systems memory map and hence it’s name.
In memory map I/O every instruction that refers to a memory location can
control I/O. The source and destination for the I/O mapped I/O is only
accumulator, however, for memory mapped I/O, there are number of
sources and destinations.
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Memory mapped I/O...
MOV R, M ; Input from a port to specified register
MOV M, R ; output specified register to the port
MVI M, DATA ; Output immediate data to the output port
LDA ADDR ; Input from a port to accumulator
STA ADDR ; Output contents of accumulator to the output port
LHLD ADDR ; Input from two ports to the HL register
SHLD ADDR ; Output HL register to the two output ports
LDAX RP ; Input from the port to the accumulator
STAX RP ; Output data from accumulator to the output port
ADD M ; Port contents are added to the accumulator
ANA M
ORA M
XRA M
CMP M
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Comparison Between Memory Mapped I/O and I/O
Mapped I/O
Memory Mapped I/O I/O Mapped I/O
In this device address is 16 bit. Thus A0 to A15 lines are
used to generate device address
In this I/O device address is 8 - bit. This A0 to A7 or A8
to A15 are used to generate device address.
MEMR and MEMW control signals are used to control read
and write I/O operations.
IOR and IOW control signals are used to control read and
write I/O operations.
Instructions available are LDA Addr, STA Addr, LDAX Rp,
STAX Rp, LHLD Addr, SHLD Addr, MOV M, R CMP M,
etc
Instructions available are IN and OUT
Data transfer is between any register and I/O device Data transfer is between accumulator and I/O device
Maximum number of I/O devices are 65536 Maximum number of I/O devices are 256
Execution speed using LDA Addr, STA Addr is 13 - T state
& 7-T states for MOV M, R and MOV R, M
Execution speed is 10 T - states
Decoding 16 bit address may require more hardware Decoding 8 bit address will require less hardware
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Types of Parallel Data Transfer or I/O Techniques
Parallel data transfers are mainly categorized into two types: Synchronous
parallel data transfer and asynchronous parallel data transfer. Main Slide

Synchronous parallel data transfer
In synchronous parallel data transfer data will be always transfer in mode
0 (8255 PPI). In synchronous parallel data transfer once the setup is es-
tablished and command is given to transfer data, data will be transferred
in continuous manner. Because of continuous manner synchronous parallel
data transfer is faster than the asynchronous parallel data transfer.
Figure : Synchronous parallel data transfer
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asynchronous parallel data transfer
In asynchronous parallel data transfer status pins are used to check the
device is ready or not. If the device is ready then data transfer is perform
otherwise operation is denied or continuously check the status. Obviously by
checking the status all the time before transferring the data asynchronous
parallel data transfer is slower then the synchronous parallel data transfer.
Figure : Asynchronous parallel data transfer

Asynchronous parallel data transfer...
Asynchronous parallel data transfer is further classified into following types:
1. Asynchronous parallel data transfer using status signal or polling or
programmed control input/output.
2. Asynchronous parallel data transfer using Ready pin or WAIT state.
3. Asynchronous parallel data transfer using interrupt or interrupt control
input/output
4. Asynchronous parallel data transfer using handshake signals
5. Asynchronous data transfer using DMA (Direct memory access) opera-
tion.
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Asynchronous parallel data transfer using status signal or polling or
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1. Asynchronous parallel data transfer using status signal or polling or
For the above example it is assume that status signal is connected with
PA7 pin of 8255 PPI. Through this port the contents on port A is
transferred to accumulator of microprocessor 8086 and by checking the
MSB (PA7) it is verified that the value of status signal is 1 or not. If
status signal is 1 then data transferring is performed otherwise operation is
stop or continuously checking of status signal is performed.
In this case the value of X is check by microprocessor using program and
hence it is also called programmed control input/output.
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2. Asynchronous parallel data transfer using Ready pin or WAIT state.
In this example microprocessor will check the signals on READY pin. If
READY pin is 1 then microprocessor will continue to normal operation and
ready to perform data transferring and when READY signal is 0 then
microprocessor will enter into WAIT state. The drawback of this type is
microprocessor is entering into WAIT state hence wasting the time of
microprocessor.
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3. Asynchronous parallel data transfer using interrupt or interrupt
control input/output
In this case if the status signal X=0 then RST 6.5 = 0 so microprocessor
is not interrupted and hence microprocessor is executes main program.
If the status signal X=1 then RST 6.5 =1 so microprocessor is interrupted
and hence microprocessor will executes ISR (Interrupt service routine) this
ISR is used to transfer the data.
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4. Asynchronous parallel data transfer using handshake signals
The handshake signals are used to ensure the readiness of the I/O device
and to synchronize the timing of the data transfer. In this data transfer,
the status of the handshaking signals are checked between the
Microprocessor and an I/O device and when both are ready, the actual
data is transferred.
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5. Asynchronous data transfer using DMA (Direct memory access)
operation.
To increase the speed of data transfer between memory and I/O, the
hardware controlled I/O is used. It is commonly referred to as direct
memory access. The hardware which controls this data transfer is
commonly known as DMA controller. The DMA controller sends a HOLD
signal to the microprocessor to initiate data transfer. In response to the
HOLD signal, microprocessor releases its data, address, and control buses
to the DMA controller. Then the data transferred is controlled at high
speed by the DMA controller without the intervention of the
Microprocessor. After data transfer, DMA controller sends low on the
HOLD pin, which gives the control of data, address and control buses
back to the microprocessor. This type of data transfer is used for large
data transfer.
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Thank you
Please send your feedback at nbahadure@gmail.com
For more details and updates kindly visit
https://sites.google.com/site/nileshbbahadure/home
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Memory interfacing of microprocessor 8085

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