Microcontroller pic 16f877 addressing modes instructions and programming

Microcontroller (PIC)
PIC Microcontroller Programming
Dr. Nilesh Bhaskarrao Bahadure
nbahadure@gmail.com
https://www.sites.google.com/site/nileshbbahadure/home
July 1, 2021
Dr. Nilesh Bhaskarrao Bahadure (PhD) Microcontroller (PIC) July 1, 2021 1 / 118

Overview
1 Syllabus
2 Course Objectives & Outcomes
3 Objectives
4 Addressing Modes
Immediate addressing mode
Register operand addressing mode
Memory operand addressing mode
Direct addressing mode
Indirect addressing mode
5 Instruction Sets of PIC16F877
Guidelines from Microchip Technology
Instruction Set:
Summary of Instructions
Encoding of instruction:
Instruction Execution Period
Pipelining of instruction fetch successive addressing
Word list
Instruction set - Group Wise

Syllabus
Unit Heading No. of Lectures
PIC Microcontroller Program-
ming
No of lectures - 5
Addressing modes, Instruction set, Assembly Language and C pro-
gramming.

Course Objectives
1 To expose the students to the fundamentals of PIC Microcontroller
16F877 architecture and its Peripherals.
2 To introduce the advanced features in PIC Microcontroller 16F877.
3 To make student develop and practice assembly language and C
language programming techniques
4 To enable student demonstrate and perform hardware interfacing and
design.

Course Outcomes
At the end of the course, the student shall be able to,
1 Describe how PIC microcontroller and its peripherals function.
2 Interpret advanced features in PIC Microcontroller 16F877.
3 Program an embedded system in assembly and C.
4 Design, implement and test a single-processor embedded systems for
real-time applications

Objectives
Upon completion of this chapter, you will be able to:
1 Understanding of addressing modes and its importance in writing
programs
2 Manipulate data using the WREG and MOVE instructions
3 Perform simple operations such as ADD and MOVE using the file
register and access bank in the PIC microcontroller
4 Code simple PIC assembly language programming
5 Details the execution of PIC assembly language instructions

Addressing Modes
To know the working principal and data handling, we need to have clear
knowledge on addressing modes of pic microcontroller. Now we can see
that how we can categorise different addressing modes of pic
microcontroller. In PIC micro controller, it having mainly five addressing
modes. Those are
1 Immediate addressing mode
2 Register operand addressing mode
3 Memory operand addressing mode
4 Direct addressing
5 Indirect addressing.

Immediate addressing mode
In this addressing mode, the operand is a number or constant not an
address as MOVLW 43h, the operand here is data not address. So in this
addressing mode of pic microcontroller data is directly transfer. And data
is immediate after the opcode. That is why this type of addressing is
called immediate addressing. This way is fast in execution.

Register operand addressing mode
In this addressing mode, the operand is a Register which holds the data to
be execute. Register operand addressing mode deals with the registers like:
CLR W

Memory operand addressing mode
In this addressing mode, the operand is an address of Memory location
which holds the data to be execute. Again memory operand addressing
mode is under two category
Direct addressing like CLRF 13h. We deal with the address or the
memory location.
Indirect addressing. we use in it INDF and FSR registers.

Direct addressing mode
Direct Addressing is done through a 9-bit address. This address is
obtained by connecting 7th bit of direct address. By using an instruction
with two bits (RP1, RP0) from STATUS register. this is shown in Figure
1. Any access to SFR registers can be an example of direct addressing.
Figure : Direct addressing mode

Indirect addressing mode
It does not take an address from an instruction. But it derives from IRP
bit of STATUS and FSR registers. Addressed location is accessed through
INDF register. And INDF register in fact holds the address indicated by
the FSR. Indirect addressing is very convenient for manipulating data
arrays located in GPR registers. In this case, it is necessary to initialise
FSR register with a starting address of the array, and the rest of the data
can be accessed by increment the FSR register. Figure 2 shows the
indirect addressing concept.

Instruction Sets of PIC16F877
We have already mentioned that microcontroller is not like any other
integrated circuit. When they come out of production most integrated
circuits are ready to be built into devices which is not the case with
microcontrollers. In order to ”make” microcontroller perform a task, we
have to tell it exactly what to do, or in other words we must write the
program microcontroller will execute. We will describe in this chapter
instructions which make up the assembler, or lower-level program language
for PIC microcontrollers.

Complete set which includes 35 instructions is given in the following table.
A reason for such a small number of instructions lies primarily in the fact
that we are talking about a RISC microcontroller whose instructions are
well optimized considering the speed of work, architectural simplicity and
code compactness. The only drawback is that programmer is expected to
master ”uncomfortable” technique of using a reduced set of 35
instructions.

The instruction sets in PIC is developed by the basis of RISC structure.
The instruction sets can be classified into 5 separate categories (depends
on the basis of type of operation). They are
1 DATA TRANSFER GROUP
2 ARITHMETIC AND LOGIC OPERATIONS GROUP
3 BIT OPERATION GROUP INSTRUCTIONS
4 PROGRAM FLOW CONTROL
5 Other instructions (Explained along with Program Flow Control)

Guidelines from Microchip Technology
For writing assembly language program Microchip Technology has
suggested the following guidelines.
1 Write instruction mnemonics in lower case. (e.g., movwf)
2 Write the special register names, RAM variable names and bit names
in upper case. (e.g., PCL, RP0, etc.)
3 Write instructions and subroutine labels in mixed case. (e.g.,
Mainline, LoopTime)

Instruction Set: I
The instruction set for PIC16C74A consists of only 35 instructions. Some
of these instructions are byte oriented instructions and some are bit
oriented instructions.
The byte oriented instructions that require two parameters (For example,
movf f, F(W)) expect the f to be replaced by the name of a special
purpose register (e.g., PORTA) or the name of a RAM variable (e.g.,
NUM1), which serves as the source of the operand. ’f’ stands for file
register. The F(W) parameter is the destination of the result of the
operation. It should be replaced by:
F, if the destination is to be the source register.
W, if the destination is to be the working register (i.e., Accumulator or W
register).

Instruction Set: II
The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here
’f’ is to be replaced by the name of a special purpose register or the name
of a RAM variable. The ’b’ parameter is to be replaced by a bit number
ranging from 0 to 7.
Example
For example: Z equ 2
btfsc STATUS, Z
Z has been equated to 2. Here, the instruction will test the Z bit of the
STATUS register and will skip the next instruction if Z bit is clear.
The literal instructions require an operand having a known value (e.g.,
0AH) or a label that represents a known value.

Instruction Set: III
Example
For example: NUM equ 0AH ; Assigns 0AH to the label NUM ( a constant
)
movlw NUM ; will move 0AH to the W register.
Every instruction fits in a single 14-bit word. In addition, every instruction
also executes in a single cycle, unless it changes the content of the
Program Counter. These features are due to the fact that PIC micro
controller has been designed on the principles of RISC (Reduced
Instruction Set Computer) architecture.

Mnemonics Description Instruction
Cycles
bcf f, b
Clear bit b of register f 1
bsf f, b
Set bit b of register f 1
clrw
Clear working register W 1
clrf f
Clear f 1
movlw k
Move literal ’k’ to W 1
movwf f
Move W to f 1
movf f, F(W)
Move f to F or W 1
swapf f, F(W)
Swap nibbles of f, putting result in F or W 1
andlw k
And literal value into W 1
andwf f, F(W)
And W with F and put the result in W or F 1
andwf f, F(W)
And W with F and put the result in W or F 1

Cycles
iorlw k
inclusive-OR literal value into W 1
iorwf f, F(W)
inclusive-OR W with f and put the result in
F or W
1
xorlw k
Exclusive-OR literal value into W 1
xorwf f, F(W)
Exclusive-OR W with f and put the result in
F or W
1
addlw k
Add the literal value to W and store the result
in W
1
addwf f, F(W)
Add W to f and store the result in F or W 1
sublw k
Subtract the literal value from W and store
the result in W
1
subwf f, F(W)
Subtract f from W and store the result in F
or W
1
rlf f, F(W)
Copy f into F or W; rotate F or W left
through the carry bit
1

Cycles
rrf f, F(W)
Copy f into F or W; rotate F or W right
through the carry bit
1
btfsc f, b
Test ’b’ bit of the register f and skip the next
instruction if bit is clear
1 / 2
btfss f, b
Test ’b’ bit of the register f and skip the next
instruction if bit is set
1 / 2
decfsz f, F(W)
Decrement f and copy the result to F or W;
skip the next instruction if the result is zero
1 / 2
incfcz f, F(W)
Increment f and copy the result to F or W;
skip the next instruction if the result is zero
1 / 2
goto label
Go to the instruction with the label ”label” 2
call label
Go to the subroutine ”label”, push the Pro-
gram Counter in the stack
2
retrun
Return from the subroutine, POP the Pro-
gram Counter from the stack
2
retlw k
Retrun from the subroutine, POP the Pro-
gram Counter from the stack; put k in W
2

Cycles
retie
Return from Interrupt Service Routine and
re-enable interrupt
2
clrwdt
Clear Watch Dog Timer 1
sleep
Go into sleep/ stand by mode 1
nop No operation 1

As has been discussed, each instruction is of 14-bit long. These 14-bits
contain both op-code and the operand. Some examples of instruction
encoding are shown here.
Example

Example
Figure : Example 2

Instruction Execution Period
All instructions are executed in one cycle except for conditional branch
instructions if condition was true, or if the contents of program counter
was changed by some instruction. In that case, execution requires two
instruction cycles, and the second cycle is executed as NOP (No
Operation). Four oscillator clocks make up one instruction cycle. If we are
using an oscillator with 4MHz frequency, the normal time for executing an
instruction is 1 µs, and in case of conditional branching, execution period
is 2 µs.

Pipelining of instruction fetch successive addressing I

Pipelining of instruction fetch successive addressing II
Figure : Pipelining of instruction fetch successive addressing

Pipelining of instruction fetch successive addressing III
Figure : Introduction of extra cycle for a jump/goto instruction

Word list
f any memory location in a microcontroller
(0x00 to 0x7F)
W work register
b bit position in ’f’ register
d destination bit (d=0:store result in W,
d=1:store result in file register f. Default
is d=1)
label group of eight characters which marks the
beginning of a part of the program
TOS top of stack
[] option
<> bit position inside register

Instruction set - Group Wise I

Instruction set - Group Wise II

1. MOVLW
MOVLW
Syntax MOVLW k
Desciption 8 - bit contents of k is written in W register
Operation k ⇒ (W )
Operand 0 ≤ k ≤ 255
Flags –
Number of words 1
Number of cycles 1

MOVLW
Example
MOVLW 0x5A
After execution: W = 0x5A
Example
MOVLW REGISTER
Before execution: W = 0x10 and REGISTER = 0x40
After execution: W=0x40

2. MOVWF
MOVWF
Syntax MOVWF f
Desciption contents of W register is copied to f register
Operation W ⇒ (f )
Operand 0 ≤ f ≤ 127
Flags –
Number of words 1
Number of cycles 1

MOVWF
Example
MOVWF OPTION REG
Before execution: OPTION REG = 0x20
W=0x40
After execution: OPTION REG = 0x40
W=0x40
Example
MOVWF INDF
Before execution: W=0x17
FSR = 0xC2
Address contents 0xC2 = 0x00
FSR = 0xC2
Address contents 0xC2 = 0x17

3. MOVF f, d
MOVF f, d
Syntax MOVF f, d
Desciption Contents of f register is stored in location
determined by d operand.
If d = 0, destination is W register
If d = 1, destination is f register itself
Option d=1 is used for testing the contents
of f register because execution of this in-
struction affects Z flag in STATUS register.
Operation f ⇒ (d)
Flags Z
Number of words 1
Number of cycles 1

MOVF f, d
Example
MOVF FSR, 0
Before execution: FSR = 0xC2
W=0x00
After execution: W=0xC2
Z=0
Example
MOVF INDF, 0
FSR=0xC2
Address contents 0xC2=0x00
FSR = 0xC2
Z=1

4. CLRW
CLRW
Syntax CLRW
Desciption Contents of W register evens out to zero,
and Z flag in STATUS register is set to one
Operation 0 ⇒ (W )
Operand –
Flags Z
Number of words 1
Number of cycles 1

CLRW
Example
CLRW
Before execution: W = 0x55
Z=1

5. CLRF
CLRF
Syntax CLRF
Desciption Contents of f register evens out to zero, and
Z flag in STATUS register is set to one
Operation 0 ⇒ (f )
Flags Z
Number of words 1
Number of cycles 1

CLRF
Example
CLRF STATUS
Before execution: STATUS=0xC2
After execution: STATUS=0x00
Z=1
Example
CLRF INDF
Before execution: FSR=0xC2
After execution: FSR=0xC2
Z=1

6. SWAPF f, d
SWAPF f, d
Syntax SWAPF f, d
Desciption Upper and lower half of f register exchange
places
If d = 0, result is stored in W register
If d = 1, result is stored in f register itself
Option d=1 is used for testing the contents
of f register because execution of this in-
struction affects Z flag in STATUS register.
Operation f < 0 : 3 >⇒ d < 4 : 7 >, f < 4 : 7 >⇒
d < 0 : 3 >
Flags –
Number of words 1
Number of cycles 1

SWAPF f, d
Example
SWAP REG, 0
Before execution: REG=0xF3
After execution: REG=0xF3
W=0x3F
Example
SWAP REG, 1
Before execution: REG = 0xF3
After execution: REG=0x3F

7. ADDLW k
ADDLW k
Syntax ADDLW k
Desciption Contents of W register are added to 8-bit
contents of k and result is stored in W reg-
ister.
Operation (W ) + k ⇒ (W )
Flags C, DC, and Z
Number of words 1
Number of cycles 1

ADDLW k
Example
ADDLW 0x15
Example
ADDLW REG
Register contents REG=0x37

8. ADDWF f, d
ADDWF f, d
Syntax ADDWF f, d
Desciption Add contents of register W to register f.
Operation (W ) + (f ) ⇒ d
Flags C, DC, and Z
Number of words 1
Number of cycles 1

ADDWF f, d
Example
ADDWF FSR, 0
FSR=0xC2
After execution: W=0xD9
FSR=0xC2
Example
ADDWF INDF, 1
FSR = 0xC2
After execution= w=0x17
FSR=0xC2

9. SUBLW k
SUBLW k
Syntax SUBLW k
Desciption Contents of W register are subtracted from
k and result is stored in W register.
Operation k − (W ) ⇒ (W )
Flags C, DC, and Z
Number of words 1
Number of cycles 1

SUBLW k
Example
SUBLW 0x03
Before execution: W=0x01, C=X, Z=X
After execution: W=0x02, C=1, Z=0
Result > 0
After execution: W=0x00, C=1, Z=1
Result = 0
After execution: W=0xFF, C=0, Z=0
Result < 0

10. SUBWF f, d
SUBWF f, d
Syntax SUBWF f, d
Desciption Contents of register W is subtracted from
register f.
Operation (f ) − (W ) ⇒ d
Flags C, DC, and Z
Number of words 1
Number of cycles 1

SUBWF f, d
Example
SUBWF REG, 1
Before execution: REG = 3, W=2, C=X, Z=X
After execution: REG = 1, W=2, C=1, Z=0
Result ¿ 0
After execution: REG = 0, W=2, C=1, Z=1
Result = 0
After execution: REG = 0xFF, W=2, C=0, Z=0
Result ¡ 0

11. ANDLW k
ANDLW k
Syntax ANDLW k
Desciption Perform operation logic AND over the con-
tents of W register and constant k and re-
sult is stored in W register.
Operation kAND(W ) ⇒ (W )
Flags Z
Number of words 1
Number of cycles 1

ANDLW k
Example
ANDLW 0x5F
Before execution: W=0xA3
Example
ANDLW REG
Before execution: W=0xA3
REG = 0x37

12. ANDWF f, d
ANDWF f, d
Syntax ANDWF f, d
Desciption Perfrom operation of logic AND over the
contents of register W and register f.
Operation (W )AND(f ) ⇒ d
Flags Z
Number of words 1
Number of cycles 1

ANDWF f, d
Example
ANDWF FSR, 1
Before execution: W=0x17, FSR = 0xC2
After execution: W=0x17, FSR = 02
Example
ANDWF FSR, 0
Before execution: W=0x17, FSR = 0xC2
After execution: W=0x02, FSR = 0xC2

13. IORLW k
IORLW k
Syntax IORLW k
Desciption Operation logic OR is performed over the
contents of W register and over 8 bit con-
stant k, and the result is stored in W regis-
ter.
Operation kOR(W ) ⇒ (W )
Flags Z
Number of words 1
Number of cycles 1

IORLW k
Example
IORLW 0x35
Before execution: W=0x9A
After execution: W=0xBF
Z = 0
Example
IORLW REG
Before execution: REG = 0x37, W=0x9A After execution: W=0x9F
Z = 0

14. IORWF f, d
IORWF f, d
Syntax IORWF f, d
Desciption Perfrom operation of logical OR over the
Operation (W )OR(f ) ⇒ d
Flags Z
Number of words 1
Number of cycles 1

IORWF f, d
Example
IORWF REG, 0
Before execution: W=0x13, REG = 0x13
After execution: W=0x93, REG = 0x13
Z=0
Example
IORWF REG, 1
Before execution: W=0x91, REG = 0x13
After execution: W=0x91, REG = 0x93
Z=0

15. XORLW k
XORLW k
Syntax XORLW k
Desciption Operation exclusive OR is performed over
the contents of W register and over 8 bit
constant k, and the result is stored in W
register.
Operation kXOR(W ) ⇒ (W )
Flags Z
Number of words 1
Number of cycles 1

XORLW k
Example
XORLW 0xAF
Before execution: W=0xB5
After execution: W=0x1A
Example
XORLW REG
Before execution: REG = 0x37, W=0xAF After execution: W=0x18
Z = 0

16. XORWF f, d
XORWF f, d
Syntax XORWF f, d
Desciption Perfrom operation of exclusive OR over the
Operation (W )OR(f ) ⇒ d
Flags Z
Number of words 1
Number of cycles 1

XORWF f, d
Example
XORWF REG, 0
Before execution: W=0xB5, REG = 0xAF
After execution: W=0x1A, REG = 0xAF
Z=0
Example
XORWF REG, 1
Before execution: W=0xB5, REG = 0xAF
After execution: W=0xB5, REG = 0x1A

17. INCF f, d
INCF f, d
Syntax INCF f, d
Desciption Increment register f by one.
Operation (f ) + 1 ⇒ d
Flags Z
Number of words 1
Number of cycles 1

INCF f, d
Example
INCF REG, 0
Before execution: W=X, REG = 0x10, Z=0
After execution: W=0x11, REG = 0x10, Z=0
Example
INCF REG, 1
Before execution: REG = 0xFF, Z=0
After execution: REG = 0x00, Z=1

18. DECF f, d
DECF f, d
Syntax DECF f, d
Desciption Decrement register f by one.
Operation (f ) − 1 ⇒ d
Flags Z
Number of words 1
Number of cycles 1

DECF f, d
Example
DECF REG, 0
Before execution: W=X, REG = 0x13, Z=0
After execution: W=0x12, REG = 0x13, Z=0
Example
DECF REG, 1
Before execution: REG = 0x01, Z=0
After execution: REG = 0x00, Z=1

19. RLF f, d

20. RRF f, d

21. COMF f, d

22. BCF f, d

23. BSF f, d

24. BTFSC f, b

25. BTFSS f, b

26. INCFSZ f, d

27. DECFSZ f, d

28. GOTO k

29. CALL k

30. RETURN

31. RETLW k

32. RETFIE

33. NOP

34. CLRWDT

35. SLEEP

Pseudo Instructions
It is the instruction used to inform the Assembler about conversion of
Assembly Program into Machine Language Program. It is also called
pseudo or dummy instruction because these instructions are not executed
by Microcontroller. Rather, they are executed by the Assembler. In other
words, we say that Assembler Directives is used for Assembling and they
are not consuming any Memory Location because they are not executed by
Microcontroller.

Pseudo Instructions... I
1 ORG: (ORIGIN)
ORG Assembler Directive is used to initialize starting Memory
Location of the program. There is no memory space allocated for the
ORG Assembler Directive. In the program, ORG is always initialized
at the beginning.
In some of the Assemblers, ORG is used instead of ORG Assembler
Directive. ORG Assembler Directive is always followed by a number
which may be represented in decimal or hexadecimal. If the given
number is in the decimal, then writing D at the end of the number is
optional. But when given number is in the hexadecimal, then put H
at the end of the number. Whenever the number is given in any
format, assembler is always converted into the hexadecimal.
FORMAT OF ORG:
ORG 100 i.e. ORG 0064H, ORG 100H, ORG $

Pseudo Instructions... II
2 DB: (Define Byte):
This Assembler Directive is used to allocate 1 Memory Location to
each byte. So one memory location is reserved. Along with DB
Assembler Directive, 8-bit number is given either in decimal, binary or
in hexadecimal. If the number is given in the decimal format, then it
is optional to end the number with ’D’. But when the number is given
in the binary format, then put B at the end of the number. If the
number is given in hexadecimal, then put H at the end of the
number. Regardless of this number system, Assembler always
converts the given number into the hexadecimal. Apart from this
number system, it is also possible to allocate or give ASCII numbers
or characters with this DB Assembler Directive. To give the ASCII
value, it always includes either in single or double Quotation mark.
Quotation mark indicates the given string represented in ASCII. Its
simple application is used to display program in LCD Screen. So we
are using DB, to save more number of bytes.

Pseudo Instructions... III
Format of DB:
DB 12((12) d means (0CH). So the starting Memory Location is
allocated.)
DB 1001 0101B (binary is represented as 95H in Hexadecimal.)
DB 45H(Given Number in Hexadecimal.)
DB ’BHEL’/ DB ”BHEL”, both are possible. Since the single
Inverted Comma is possible in Simulator and the Double Inverted
Comma is possible.
For example: ORG 0500H
0500H → DATA1: DB 45H, 67H, 01H.
Given the Data starting memory Location is 0500H.

Pseudo Instructions... IV
3 EQU: (EQUATE)
This Assembler Directive is used to assign constant value to any
value. For example: Label EQU 1000H, then after executing this, the
value of Label becomes 1000H.
Format:
Label EQU value or Expression which may be Register, Accumulator,
Jump.
Use of Equate:
Consider the example of Counter Value. Assume Counter value is 25,
then using EQU it may be defined as
COUNT EQU 25
MOV R2, #Count

Pseudo Instructions... V
4 END
END means the end of Assembly Process. So, no instruction either
belonging to Assembler or microcontroller is executed after END.
END gives only once in a program and that to be in the last
indicating end of Assembly Process. Some Assembler will Support
.END instead of END Assembler Directive.
5 SET
This directive is used to define a constant value or a fixed address. In
this regard, the SET and EQU directives are identical. The only
difference is the value assigned by the SET directive may be
reassigned later.

Pseudo Instructions... VI
6 LIST directives
Unline ORG and END, which are used by all assemblers, the LIST
directive is unique to the PIC assembler. It indicates to the assembler
the specific PIC chip for which the program should be assembled. It is
used as follows:
LIST P = 16F877
The above tells the PIC assembler to assemble the program
specifically for the PIC16F877 microcontroller. We use LIST to state
the target chip.
7 #include directive
The #include directive tells the PIC assembler to use the libraries
associated with the specific chip for which we are compiling the
program.

Pseudo Instructions... VII
8 config directive
The config directive tells the assembler the configuration bits for the
targeted PIC chip.
9 radix directive
we can use the radix directive to indicate whether the numbering
system is hexadecimal or decimal. The default is hex if we do not use
the radix directive.
Example: radix dec

Assembly and C Language Programming
Program 1
Write an assembly language programming to add two 8-bit numbers 28h
and 56h and store the result in register W.
Solution
Instructions Comments
movlw 0x28 ; copy data 28h to the W register
movwf 0x20 ; copy contents of W register to memory location/file reg-
ister 20h
movlw 0x56 ; copy data 56h to the W register
addwf 0x20, 0 ; add contents of W register with the contents of file register
20h and store the result in W register
goto $ ; stop execution

Simulation - Program 1

Program 2
Write a program to copy the value 55H into RAM locations 40h to 44h
using
(A) Direct addressing mode
(B) Register indirect addressing mode
(C) A loop

Solution - (A)
org 0x0004 ; interrupt vector location
main: ; start of program
MOVLW 0x55 ; copy data 55h to W register
MOVWF 0x40 ; copy contents of W register to memory location/FSR 40h
MOVWF 0x41
MOVWF 0x42
MOVWF 0x43
MOVWF 0x44
goto $

Solution - (B)
main: ; start of program
MOVLW 0x55 ; copy data 55h to W register
MOVWF 0x40 ; copy contents of W register to memory location/FSR 40h
MOVWF 0x41
MOVWF 0x42
MOVWF 0x43
MOVWF 0x44
goto $

Program 3
Write an assembly language programming to add two 16-bit numbers
present in the memory location 21h-20h and 31h-30h and store the result
in memory location 31h-30h.

Solution
org 0x0000
x EQU 0x20 ; Define memory location 20h
y EQU 0x30 ; Define memory location 30h
nop ; nop required for icd
goto main ; go to beginning of program
main:
movf x,W ; copy contents of 20h to reg W
addwf y,f ; Add contents of Reg W and Mem Loc 30h and store result in ML 30
btfsc STATUS,C ; Check for carry if C = 1 add 1 to the contents of ML 30h
incf y+1,f
movf x+1,W ; copy contents of ML 21h to Reg W
addwf y+1,f ; Add contents of Reg W and Mem Loc 31h and store result in ML 31

Program 4
Write an assembly language programming to add two 32-bit numbers
present in the memory location 23h to 20h and 33h to 30h and store the
result in memory location 33h to 30h.

Solution
org 0x0000
main:

Solution
movf x,W
addwf y,f ; add byte 0 (LSB)
movf x+1, W
btfsc STATUS, C
incfsz x+1, W
addwf y+1,f ; add byte 1
movf x+2, W
btfsc STATUS, C
incfsz x+2, W
movf x+3, W
btfsc STATUS, C
incfsz x+3, W

Program 5
Write an assembly language programming to subtract two 16-bit numbers
present in the memory location 21h-20h (LSB) and 31h-30h (MSB) and
store the result in memory location 31h-30h.

Solution
org 0x0000
main:
movf x, W ; copy contents of ML 20h to Reg W
subwf y, f ; subtract LSB y-w put result in y
movf x+1, W ; get MSB
btfss STATUS, C ; if borrow from LSB subtraction
incfsz x+1, W ; increment copy of MSB
subwf y+1, f ; subtract MSB

Program 6
Write an assembly language programming to subtract two 32-bit numbers
present in the memory location 23h to 20h and 33h to 30h and store the
result in memory location 33h to 30h.

Solution
org 0x0000
main:

Solution
movf x,W
subwf y,f ; subtract byte 0 (LSB)
movf x+1, W
btfss STATUS, C
incfsz x+1, W
subwf y+1,f ; subtract byte 1
movf x+2, W
btfss STATUS, C
incfsz x+2, W
movf x+3, W
btfss STATUS, C
incfsz x+3, W

Que - 1
2017 (SLR - TJ-205) - Marks 1
The CALL and GOTO instruction provides . . . . . . bits of address to allow
branching within any . . . . . . program memory page.
(a) 13 bit, 8k
(b) 16 bit, 64k
(c) 11 bit, 2k
(d) none of these
Answer
(c) 11 bit, 2k

Que - 2
2017 (SLR-VB-179) - Marks 4
Explain the logical instructions named as XORLW, XORWF, IORLW AND
IORWF
Answer
Explain instructions 13, 14, 15 and 16

Que - 3
2016 (SLR-EP-142) - Marks 1
Before execution of ANDLW 0x5F the working register contents were
0xA3. The contents after execution will be
(a) 0x5F
(b) 0x03
(c) 0xFF
(d) none of these
Answer
(b) 0x03

Que - 4
2016 (SLR-EP-142) - Marks 5
Explain logical instructions related to PIC
Answer
Explain instructions 11, 12, 13, 14, 15 and 16

References
[1, 2, 3, 4]
Muhammad Ali Mazidi, Rolin D. McKinlay, and Danny Causey.
PIC Microcontroller and Embedded Systems - Using Assembly and C
for PIC18.
Pearson International Edition, Upper Saddle River, NJ, 2008.
Martin P. Bates.
Programming 8 - bit PIC Microcontrollers in C with Interactive
Hardware Simulation.
Newnes Press Private Limited, United Kingdom, 2008.
Ajay V. Deshmukh.
Microcontrollers Theory and Applications.
Tata McGraw Hill, New Delhi, India, 2008.
John B. Peatman.
Design with PIC Microcontroller.
Prentice Hall, New Delhi, India, 1997.

Thank you
Please send your feedback at nbahadure@gmail.com
For download [Click Here]

Microcontroller pic 16f877 addressing modes instructions and programming

More Related Content

What's hot (20)

Similar to Microcontroller pic 16f877 addressing modes instructions and programming (20)

More from Nilesh Bhaskarrao Bahadure (20)

Recently uploaded (20)

Microcontroller pic 16f877 addressing modes instructions and programming