MIPI DevCon 2021: MIPI I3C Signal Integrity Challenges on DDR5-based Server Platform Solutions
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The document discusses the signal integrity challenges associated with implementing the MIPI I3C interface in DDR5-based server platforms, focusing on factors such as bus capacitance and the transition from I2C to I3C. It elaborates on various technical aspects, including buffer design, critical timing margins, and the interoperability between open-drain and push-pull modes to enhance system performance. Recommendations include using dynamic pull-ups, strong drive buffers, and Schmitt trigger inputs to address challenges posed by higher capacitance in server applications.
MIPI DevCon 2021: MIPI I3C Signal Integrity Challenges on DDR5-based Server Platform Solutions
- 1. © 2021 MIPI Alliance, Inc. Azusena Lupercio Juan Orozco Nestor Hernandez Intel Corporation I3C® Signal Integrity Challenges on DDR5 Based Server Platform Solutions
- 2. © 2021 MIPI Alliance, Inc. 2 • Introduction • DDR5 SPD server connectivity and bus characteristics • I2C and MIPI I3C Retro-compatibility challenges – Non-dynamic pullup impact – Dynamic pullup on open-drain • Buffer RON design implications • Critical time margin calculation – Frequency and AC/DC parameters impact • Non-monotonic signal behavior • Slope reversal capability and timing improvement • Summary Agenda
- 3. © 2021 MIPI Alliance, Inc. Introduction
- 4. © 2021 MIPI Alliance, Inc. 4 Introduction • The MIPI I3C Improved Inter-Integrated Circuit interface is first introduced in a server application for the DDR5 DIMM Serial Presence Detect (SPD) function. • Its implementation exceeds by far the bus capacitance/loading specification, which was defined for low capacitance Mobile/IoT applications. • This presentation covers the interoperability challenges of the dynamic push-pull and open-drain operating modes on I3C BASIC server applications. – Covering an in-depth analysis of the implications of long PCB traces, multiple DIMM routing branches, several loads, to the electrical and timing parameters.
- 5. © 2021 MIPI Alliance, Inc. 5 Introduction cont'd • I3C Communication Bus specification was released by MIPI Alliance in 2016, as an improved communication protocol compared to its predecessor I2C, but the implementation of I3C, in a Data Center (Server) application was materialized until 2020. • The main enhancements in I3C adopted by the DDR SPD function are: – Higher bit rate: up to 12.5MHz, compared to 100KHz-1MHz I2C SPD in prior DDR generations (125x to 12.5x higher bit rate). – Better IO electrical interface: Push-pull driver vs Open Drain only. – In-band interrupts (IBI) support – Not supported in DDR5 now, but looking for support in the future (or in other Server use cases). – In band Common Command Codes (CCCs) – Direct or Broadcast. – Reduced interface power (1.0V IOs).
- 6. © 2021 MIPI Alliance, Inc. 6 Introduction cont'd • The DDR5 SPD interface transitioned from I2C to MIPI I3C based on the following requirements for the next generation DDR DIMM technology: – Lower IO operating Voltage (as low as 1V aligned to advanced process node) • DDR4 SPD IO voltage was 2.5V – Higher interface bit rate (400KHz to 8-12.5MHz in real applications) due to the increased number of devices per DIMM to be managed • DDR4 had two devices per DIMM vs five devices in DDR5 • Considering 8 DIMMs per SPD segment, this is 16 vs 40 devices – Higher bit rate to reduce boot time (diminishing Memory Reference code execution time)
- 7. © 2021 MIPI Alliance, Inc. DDR5 SPD Server connectivity and bus characteristics
- 8. © 2021 MIPI Alliance, Inc. 8 DDR4 vs DDR5 SPD DIMM Connectivity • DDR4 SPD • DDR5 SPD SPD Memory and Temp Sensor (TS) Registering Clock Driver (RCD) I2C Platform Interface (2.5V) Level Shifter I2C Platform Controller (CPU or BMC) I2C Platform Controller (1.0V or 3.3V) SPD I3C HUB and Memory Registering Clock Driver (RCD) I3C Platform Interface (1.0V) I3C Platform Controller (CPU or BMC) Power Management IC (PMIC) Temperature Sensor #1 (TS1) Temperature Sensor #2 (TS2) Host Side Interface Local Side Interface Provides isolation and transparent communication from the Host to the Local devices (5pf per device)
- 9. © 2021 MIPI Alliance, Inc. 9 DDR4 vs DDR5 SPD DIMM Connectivity • DDR4 SPD • DDR5 SPD SPD Memory and Temp Sensor (TS) Registering Clock Driver (RCD) I2C Platform Interface (2.5V) Level Shifter I2C Platform Controller (CPU or BMC) I2C Platform Controller (1.0V or 3.3V) SPD I3C HUB and Memory Registering Clock Driver (RCD) I3C Platform Interface (1.0V) I3C Platform Controller (CPU or BMC) Power Management IC (PMIC) Temperature Sensor #1 (TS1) Temperature Sensor #2 (TS2) Host Side Interface Local Side Interface Introduces a time delay (12ns round trip) between Host and Local Devices
- 10. © 2021 MIPI Alliance, Inc. DDR5 SPD Bus Characteristics
- 11. © 2021 MIPI Alliance, Inc. 11 DDR5 SPD Platform Connectivity CPU CPU BMC 8x DIMMs ~16" 19" • Host side Server PCB routing – Total length could exceed 50” • Server motherboards are BIG: up to 16”x 19” • BMC controller is located at the North side • DIMMs are located at the South side • CPU to DIMM SPD routing has lower priority than high speed IO routing (DDR5, PCIe G4/G5, etc.)
- 12. © 2021 MIPI Alliance, Inc. 12 Routing length and capacitance • Host side Server PCB routing – From Controller to DIMMs (L11+L12+L2x): ~25” – DIMM routing (LDIMM): 3.5”/DIMM, 28” 8x DIMMs – Total PCB trace length: ~53” • Host side Total Capacitance – Each device apports 5pF • 1 CPU + 8 HUBs =45pF – PCB routing is ~3pF/in • 53” * 3pF = ~159pF – Totaling: • Dev (45pF) + PCB (53pF) =~204pF Controller DIMM Connector #1 DIMM 1 L DIMM RDIMM DIMM Connector #2 DIMM 2 L DIMM RDIMM DIMM Connector #3 DIMM 3 L DIMM RDIMM L22 L23 L11 1.0V L12 RS DIMM Connector #8 DIMM 8 L DIMM RDIMM L28 I3C SPD HUB I3C SPD HUB I3C SPD HUB I3C SPD HUB RPU-HK 1.0V RPU-OD
- 13. © 2021 MIPI Alliance, Inc. I2C and MIPI I3C Retro-compatibility Challenges
- 14. © 2021 MIPI Alliance, Inc. 14 • There are three operating modes supported by the I3C protocol: – I2C mode with Open-Drain(OD) buffer class. – I3C mode with Open-Drain buffer class. – I3C mode with Push-Pull(PP) buffer class. • The OD class requires a pullup to set a stable “Logic-high”. • The pullup is set accordingly with the total capacitance on the bus. • High capacitance busses requires a “Strong pullup” – Strong pullup guarantees rise time specification to pass. • The PP class requires a High-Keeper pullup. – A “Weak pullup” is required to the target device with low current can pull SDA signal low within a minimum low period. – Weak pull-up lessens the voltage levels disturbances I2C and MIPI I3C Retro-compatibility Challenges MIPI I3C Basic Spec requires Dynamic pull-up control to switch between “strong pull-up” and “weak pull-up” to optimize open-drain and push-pull timing requirements.
- 15. © 2021 MIPI Alliance, Inc. 15 Non-Dynamic Pullup impact in a 204pF bus The Highest the PU – VIH never reached with pull-up higher than 800Ω • Limit max operating frequency Open-Drainà ßPush-Pull 5.8 5.9 6 6.1 0 1000 2000 3000 4000 Time (ns) Pull-up Resistor (Ohms) Rise Time Clock 8.4 8.6 8.8 9 9.2 0 1000 2000 3000 4000 Time (ns) Pull-up Resistor (Ohms) Fall Time Clock -0.02 0 0.02 0.04 0.06 0.08 0 1000 2000 3000 4000 Voltage (V) Pull-up Resistor (Ohms) Voltage Output Low (VOL) 120.6 0 40 80 120 160 200 200.0 300.0 400.0 500.0 600.0 700.0 800.0 Time (ns) Pullup (Ohms) Rise Time Clock OD 6 7 8 9 10 200.0 400.0 600.0 800.0 Time (ns) Pullup (Ohms) Fall Time 0 0.05 0.1 0.15 200.0 400.0 600.0 800.0 Voltage (V) Pullup (Ohms) Voltage Output Low Rise time increases Fall time decreases VOL decreases Rise time increases Fall time decreases VOL decreases The Highest the PU – VIH never reached with pull-up higher than 800Ω • Limit max operating frequency • On-Board PU can guarantee an OD max operating frequency. – A parallel equivalent RPU_HK ||RPU_OD of 333.3Ω • Rise time=75.3ns • A pullup ≥ 550Ω negatively affects both rise time and operating frequency A trade-off among pull-up value, rise time and VOL is required to meet the highest operating frequency
- 16. © 2021 MIPI Alliance, Inc. Buffer RON design implications
- 17. © 2021 MIPI Alliance, Inc. 17 Buffer RON value design implications • The bigger the RON the higher the VOL is: – Increasing trace length results in higher VOL • With the longest trace length, VOL= 192mV, – Assuming VIL=0.3V then the transition margin is 108mV » Low transition margin can cause idle states • Setting the RON at 40Ω reduces the VOL • With the longest trace length VOL= 146mV, – If VIL=0.3V then the transition margin is 154mV • Notice that at the longest trace length with VOL=146mV the IOL is 3.66mA 0.1464 0.192 0 0.05 0.1 0.15 0.2 0.25 0 10 20 30 40 50 Voltage (V) Trace length (inches) RON impact on VOL Ron=20 ohms Ron=40 ohms Ron=100 ohms 3.66 0 1 2 3 4 5 6 7 0 10 20 30 40 50 Current (mA) Trace length (inches) RON impact on IOL Ron=20 ohms Ron=40 ohms Ron=100 ohms By limiting Ron into a max range of 40Ω ensures a healthy VOL by setting a max IOL bigger than 3mA
- 18. © 2021 MIPI Alliance, Inc. Critical time margin calculation
- 19. © 2021 MIPI Alliance, Inc. 19 Critical time margin calculation Tco_DATA_TARGET tLOW Tflt_DATA_TARGET-HUB Tpd_DATA_HUB Tflt_DATA_HUB-PRIMARY Tflt_CLK_PRIMARY-HUB Tpd_CLK_HUB Tflt_CLK_HUB-TARGET Tsu_PRIMARY Tsu_margin PRIMARY_CLK PRIMARY-HUB_CLK HUB_CLK HUB-TARGET_CLK TARGET_DATA TARGET-HUB_DATA HUB_DATA PRIMARY_DATA TARGET driving to PRIMARY:Setup margin TARGET driving to PRIMARY: Setup margin TARGET PRIMARY CLK DATA CLK DATA SPD HUB CLK DATA CLK DATA
- 20. © 2021 MIPI Alliance, Inc. 20 Critical time margin calculation Frequency 10 MHz Duty cycle 35 % tLOW 65 ns tflt_CLK_PRIMARY-HUB_fall 19.1 ns tpd_CLK_HUB 6 ns tflt_CLK_HUB-TARGET_fall 4.7 ns tco_DATA_TARGET 12 ns tflt_DATA_TARGET-HUB_rise 1.972 ns tpd_DATA_HUB 6 ns tflt_DATA_HUB-PRIMARY_rise 9.8 ns tsu_PRIMARY_max 3 ns Setup Margin 2.253 ns • The longer trace length the biggest flight time • Inner device propagation delay plays a significant role in defining the operating frequency. – The highest the Tpd the bigger the time margin reduction. • Increasing tLOW provides extra timing margin. -20 -10 0 10 20 30 40 0 5 10 15 20 25 30 35 40 TIME (NS) TRACE LENGTH (INCHES) TIME MARGIN 8MHz 10MHz 12.5MHz 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 TIME (NS) TRACE LENGTH (INCHES) FLIGHT TIME 10MHz Tflt_CLK_PRIMARY-HUB_fall 10MHz Tflt_CLK_HUB-TARGET_fall 10MHz Tflt_DATA_TARGET-HUB_rise 10MHz Tflt_DATA_HUB-PRIMARY_rise
- 21. © 2021 MIPI Alliance, Inc. 21 Frequency and AC/DC parameters impact -10 0 10 20 30 30 35 40 45 50 Time (ns) Duty Cycle (%) Duty Cycle impact on Time Margin 8MHz 40 inches 10MHz 30 inches 12.5MHz 2 inches • Increasing duty cycle reduces tLOW, thus reducing the Time Margin. • When reducing the Duty Cycle the tHIGH and tDIG_HIGH are affected. – Small Duty Cycle can produce a NOT PASS on tHIGH/tDIG_HIGH. 20 24 28 32 36 40 44 48 35 37 39 41 43 45 Time (ns) Duty Cycle (%) Duty Cycle impact on Clock High Period 8MHz 40 inches 10MHz 25 inches 12.5MHz 2 inches 20 24 28 32 36 40 44 48 52 56 60 35 37 39 41 43 45 Time (ns) Duty Cycle (%) Duty Cycle impact on Clock DIG High Period 8MHz 40 inches 10MHz 25 inches 12.5MHz 2 inches From MIPI I3C Spec tHIGH min 24ns, tDIG_HIGH min 32ns A correct selection of Duty Cycle provides extra time margin to complete the setup transaction, granting higher operating frequency.
- 22. © 2021 MIPI Alliance, Inc. Non-monotonic signal behavior
- 23. © 2021 MIPI Alliance, Inc. 23 Non-monotonic signal behavior • Termination effect on transmission lines – Non-terminated circuit: • Signal bounces back and forth between the driver and the receiver. – Tx-terminated circuit: • Reduces drive strength • Increases propagation delay • Limits buffer capabilities – Rx-terminated circuit: • Reduces bouncing effect • Increases propagation delay
- 24. © 2021 MIPI Alliance, Inc. Slope reversal capability and timing improvement
- 25. © 2021 MIPI Alliance, Inc. 25 Slope reversal capability and timing improvement • With the non-deterministic loading of an unterminated bus, there can be reflections on the bus causing slope reversal on the Rx signal. • By sampling at the first threshold is possible to filter Non-Monotonicity's; Schmidt triggered inputs – Non-terminated VS Rx-Terminated: Improves 2.3ns – Non-terminated VS Tx-Terminated: Improves 3.92ns Slope reversal capability provides additional time margin that improves operating frequency and prevent false logic states.
- 26. © 2021 MIPI Alliance, Inc. Summary
- 27. © 2021 MIPI Alliance, Inc. 27 Summary • I3C Applications in Server systems (such as DDR5 SPD) are dealing with higher Bus capacitance than the max limit assumptions in MIPI spec (for 12.5MHz capable buses). • Higher Bus capacitance applications can be mitigated by using good Buffer Drive strength, strong open-drain class pull-up, and HUB isolation circuits. • A dynamic pullup operation allows to drive the interoperability challenges between the open-drain and push-pull operating modes; by enabling higher operating frequencies on both modes and limiting critical parameters to meet latest specification. • Strong buffers tend to increase signal energy reflections, specially in complex topologies resulting with slope reversal conditions at Devices' Inputs. • Schmitt trigger capable inputs are required in order to mitigate slope reversal conditions when dealing with high bus capacitance and strong buffers
- 28. © 2021 MIPI Alliance, Inc.