Module 1 - ARM 32 Bit Microcontroller

ARM Microcontroller and
Embedded Systems
Prof. Amogha B
Asst Prof.
Dept. of ECE
Visvesvaraya Technological University, Belagavi.
Jain Institute of Technology, Davangere.
(A Unit of Jain Group of Institutions, Bangalore)

Brief about subject
• Module 1-
• Module 2-
• Module 3-
• Module 4-
• Module 5-
C:UsersAmoghaDesktop15EC62.pdf
2Dept. of ECE, JIT, Davangere

Before entering the syllabus
• Shall see about the some of the basics
• A general Discussion
• IF X bits controller means what
– Microprocessor 64 bit
– Microcontroller 8 , 16, 32 bits
• Think

ARM Microcontroller
• ARM founded in November 1990
– Advanced RISC Machines
– 32 bit Microcontroller
• Company headquarters in Cambridge, UK
– Processor design centers in Cambridge, Austin, and Sophia
Antipolis. (They won’t manufacture Micro-controllers)
– Sales, support, and engineering offices all over the world
• What RISC means- Reduced Instruction Set Computer
• What CISK means-

RISK and CISC
CISC RISC
Full form Full form
Includes multi clock for complex instr. Single clock
Load and store is used for memory to
memory
Register to register
Small code size Large code size but time for execution
remains same

ARM
• Assembly for arm we write only for
understanding the architecture.
– Beyond add/sub everything becomes complex and its
lost.
• ARM cortex are not mean for writing assembly
they actually not designed for it. Critically mean
for C
• With C coding it becomes more Powerful.

1st Critical thinking of ARM developers
• They made 32 bit memory access
• During the launch of ARM all other companies
were on 16bit and almost all the instructions
are 16bit.
• Memory under utilization 60-70% hence
Thumb mode.
• ARM with pipelined makes 2 instructions to
run as 32bit which makes it faster.

Thumb mode
• It became too much famous almost famous as
cortex all instructions executes at faster rate.
Problem of THUMB
• It doesn’t support all the instructions of ARM
• When thumb doesn’t supports it should
switch to ARM mode hence for switching it
became overhead.

THUMB2
• To address this they have came up with hybrid
architecture it is called as thumb 2
• This architecture is not having switching issue
and it is in ARM-CORTEX series.
• Important for working it access 16 bit memory
and carries work or process in ARM
architecture.

Graph

Cortex has three division
• CORTEX A – application specific such as
OS(IOS, android or windows) mobile phones
applications.
• CORTEX M- Microcontroller a general purpose
widely used.
• CORTEX R- Real time applications in medical
and defense sectors.
– Hardware support ex: Controller supports adder
means ?????

What ARM supplies and what partners
of ARM performs

Architecture In detail (SEE IN NEXT
SLIDES)
AMBA – 1996
Advanced
Microcontroller
Bus Architecture

Halfword and
signed halfword /
byte support
System mode
Thumb
instruction set
(v4T)
Improved
interworking
Saturated arithmetic
DSP MAC instructions
Extensions:
Jazelle (5TEJ)
SIMD Instructions
Multi-processing
v6 Memory architecture
Unaligned data support
Extensions:
Thumb-2 (6T2)
TrustZone® (6Z)
Multicore (6K)
Thumb only (6-M)
 Note that implementations of the same architecture can be different
 Cortex-A8 - architecture v7-A, with a 13-stage pipeline
 Cortex-A9 - architecture v7-A, with an 8-stage pipeline
Thumb-2
Architecture Profiles
7-A - Applications
7-R - Real-time
7-M - Microcontroller
v4 v5 v6 v7
Development of the ARM Architecture

Nomenclature of ARM (Naming)
CRITICALLY Imp.

Difference
• Simulation
– Ex: Dr driving game is a excellent example
• Emulation
– Games played at M2
• Some works in simulation but fails in real
world
• Which works in Emulation works everywhere.
• 8051 was not having EMULATOR/ ICE on
board.

4 Critical Thinking made ARM to stand
1st
Why its called a wonderful architecture and it
proved to be same.
4. Interrupts nested ( upto 240).

Oscillators
• Three oscillators
• External
• Internal
• RTC- Real Time Clock

Interrupts
• What is interrupts?
• Ex:

What is blue screen
• Hint : fatal error

Exception
• Invalid behavior are identified by ARM and
provided to user.

Which company focus on CISK
architecture
download.png

Assembly program structure
• Area – directive which allocates the memory for
code and data
• Program name- it should be different for code
and data
• Entry – start of program
• Export label_name (practical)
• End- of program
• Important thing is have one endless loop in
embedded systems.

Lets write some simple code
• For instance adding two number and store in
another register
• Mov r0, #5 ; it can access only registers not
memory
• ADD r0, r1, r2 ; r0 = r1 + r2
• Load instruction LDR
– Load to memory
– Pseudo information
• Store instruction STR
– Store from memory to register.

Structure of C with ARM
• Include lpc17xx.h
• Global variables or define
• Int main()
• Main program
• To write code in any language we need to know
– Keyword
– Looping or syntax
– Logic ( Most Important)

OUTLINE
• Thumb-2 technology and applications of ARM,
• Architecture of ARM Cortex M3,
• Various Units in the architecture, Debugging
support,
• General Purpose Registers, Special Registers,
exceptions, interrupts, stack operation, reset
sequence

Introduction
• The market of the microcontroller is vast every year 20 billions are
manufactured and they are released for sale.
• In the competitive world to meet the industrial demands the microcontrollers
should posses higher performance.
•Ex: Performing more work without increase in the clock frequency
•It should support communication peripherals such as USB, UART, Ethernet
etc.
•Enhance the user interface, multimedia requirements, system speed etc.
•In 2006 the ARM CORTEX family have entered into market
•Cortex M3 made a excellent performance with less gates (12,000) which
covers features of the previously launched high-end controllers.

Market demands for 32bit
Microcontroller
• Greater Performance Efficiency : with less power
and frequency should need more work
• Interrupt latency
• Improved code density
• Easy to use : migrating of programs from 8 to 32
bit
• Lower cost : less than a dollar
• Wide choice of development tools : companies
must posses evaluation and full version of
compliers.
Dept. of ECE, JIT, Davangere 28

Cost saving
• Cortex provided a greater success compared
to other vendors (Texas, ATMEL etc)
• Developers are towards decreasing overall
system cost.
• ARM cortex replaces a 4 traditional controllers
• Code re-use in applications which reduces
testing (Mi phone cost is less) and
development time.

Partners for ARM
• NXP, TEXAS, ATMEL, OKI.
• Before CORTEX, the most successful
controller from ARM was ARM7
• 1 billion microcontrollers are produced every
year
• Attractive features in CORTEX M3
– Nested interrupt up to 240.
– Memory Protection Unit

Instruction Enhancement

Thumb2 Technology
It is the super set of
previous 16bit thumb
instruction with extra
16bit instruction.
Why people gone for thumb 2 ?

Thumb 2 Technology
• Extended version of Thumb Instruction Set
Architecture (ISA)
• Benefits
– Ease to use no overhead of switching
– Code size is less
– Performance is more as it has both the instruction 16
and 32 bit.
• The efficiency is enhanced by decreasing the
number of switches between ARM and thumb

Compactable of Cortex M3
• Supports only thumb2 to reduce memory and
size of processor (core).
• All instructions are executed using Thumb2
hence it not backward compatible with older
ARM.

Example illustration
• In ARM7 or ARM9 processor if there are 16 and 32 bit
they need to have a switching and code length has also
increased.
• As cortex M3 supports both 16 and 32 bit there is no
overhead, higher efficiency and code length also
decreases.
• Feature:
– Hardware divide support
– Multiplication
– Data crunching performance – large data processing
(Hadoop)
– Unaligned data access is included which were in high end.

Application of CORTEX M3
• Low Cost microcontroller: lower power, less cost and
most important ease to use made people to choose
this.
• Automotive: has lesser interrupt latency and supports
upto 240 interrupts hence adopted in automotive
industry.
• Data Communication: bluetooth, zigbee, modem,
serial communications are supported.
• Industrial Control: fast response are needed hence it is
needed.
• Consumer Products: Memory protection unit as per
customer security.

Architecture of ARM Cortex M3
2 stairs but reaches
common terrace.
Back : Conti.

Conti.
• Fundament: 32bit Microcontroller means
32bit register, memory interface and data path
• Harvard architecture hence performance
increases.
• It has a multiple bus interface but shares a
common memory i.e. 8GB
• Complex application requests more memory
features i.e secure of data cortex provides
Memory Protection Unit (MPU).

Conti.
• External cache if required
• Supports both little and big endian memory
• Debugging support such as breakpoints and
watchdog at software and hardware ( through
debugging interface )

Components of Architecture
• Registers Register_bank_tecxtbook.JPG
• Ro- R15 registers ; R0 – R12 general purpose
• Low and high registers.
• Low Registers – R0 to R7- based on access

Stack Pointers- R3
• In cortex M3 has two stack pointer, they are
combined and one is visible at once.
– Main Stack Pointer (MSP)
– Process Stack Pointer (PSP)
• The lowest two bits are zero which says that
they are word aligned.

Main Stack Pointer
• The stack is a memory structure where your
programs can store data. The stack pointer is
the variable that "points" to the current
location of the top of the stack.
• MSP is the default stack pointer used in OS
and exception handling

Processor Stack Pointer (PSP)
• In all modes its runs on Main Stack Pointer but
during only SUPERIOR CALLS ( It is one of the
mode where OS allows to access all the
system resources)
• In User application codes the PSP are used.

Link Register- R14
• It stores the return information for
subroutines, function calls, and exceptions.
• On reset, the processor sets the LR value
to 0xFFFFFFFF.

Program Counter- R15
• The Program Counter (PC) is accessed by PC (or R15). It
is incremented by the size of the instruction executed
(which is always four bytes).
• Branch instructions load the destination address into
PC. You can also load the PC directly using data
operation instructions. For example, to branch to the
address in a general purpose register, use:
– MOV PC,R0
• During execution, PC does not contain the address of
the currently executing instruction.

Special Registers

Types of Special Registers
• There are three types of Special Registers
– Program Status Registers (PSRs)
– Interrupt Mask Registers.
– Control Register.

Types.
• PSR- Provide arithmetic and logic processing flags (zero flag and
carry flag), execution status, and current executing interrupt
number.
• N Negative
• Z Zero
• C Carry/borrow
• V Overflow
• Q Sticky saturation flag (Stack is overflow or saturation )
• ICI/IT Interrupt- Continuable Instruction (ICI) bits, IF-THEN
instruction status bit
• T Thumb state, always 1; trying to clear this bit will cause a fault
exception
• Exception number Indicates which exception the processor is
handling

Interrupt Mask & Control Registers
• Types
– PRIMASK – Disable all interrupts except the non-
maskable interrupt (NMI) and hard fault.
– NMI – example: warning of high tides.
– FAULTMASK- Disable all interrupts except the NMI
– BASEPRI- Disable all interrupts of specific priority
level or lower priority level
• Control Register - Define privileged status and
stack pointer selection.
• Interrupt Masking

Operating Mode

Operating Mode
• Two modes
– Operation mode – Thread mode and handler mode
– Privilege Level – privileged and user mode.
• Operation mode- used to determine processor is
running in normal(main program) or in exception
such as interrupt program.
• Thread mode(normal) is entered when the reset
is pressed or program return from exceptions.

Handler Mode
• Handler mode will be entered as a result of an
exception.
• During this mode core enters to privilege
mode
• During privileged mode any memory can be
accessed but except memory reserved by
MPU(Memory Protection Unit)

Privileged and User Mode
• Privileged – this is a mode where code is
provided with a full stretch access to memory
except MPU memory.
• USER mode- it has a limited access rights.

Switching of Privileged and User
•If program in privileged in can be switched to user but reverse is not possible.
• By having this unauthorized person can't alter system configuration (boot sequence,
boot services, listing I/O, OS data and programs)
•ANDORID : Applications in user mode initially once user provides access they can
use it.
•Location access by GPS to MAPS application.
•ShareIt : if hotspot access is provided it connects to other user or else no.

Nested Vectored Interrupt Controller
(NVIC)
• Features
– Nested interrupt support
– Vectored interrupt support
– Dynamic priority changes support
– Reduction of interrupt latency
– Interrupt masking

Nested Interrupt Support
• What is nested means
• NVIC supports nested interrupt support
• Programmed (S/w) priority given for all interrupts
• Working
– When interrupt occurs NVIC compares the priority of
the running with occurred interrupt.
– If the new interrupt is higher than current interrupt
then execution switches to the new interrupt request.
• This is called as nested.

Vector Interrupt Support
• Posses less time to serve interrupt request.
• Cortex M3 supports Vector Interrupt.
• The difference is when interrupt occurred
starting address of ISR is loaded from Vector
table.
• Hence software is not needed find the starting
address of ISR. Hence time required to serve is
less

Dynamic Priority Changes Support
• During the runtime the priority of the
interrupt can be varied.
• Till the updating of priority the current serving
of ISR is blocked
• Priority can be changed without any risk
during run time.

Reduction of Interrupt Latency
• Automatic saving and restoring some register
contents, reducing delay in switching from one
ISR to another.
• How
– The processor automatically stacks its state on
exception entry and un-stacks previous state on
exception exit, with no instruction overhead. This
provides low latency exception handling.

Interrupt Masking
• Based on the priority level the interrupts are masked.
Masked means
• Providing the priority level to each interrupt
• Non-Masking interrupts means
– These types of interrupts are never ignored by system.
• The masking registers takes care that time critical tasks
should finish within pre-allotted time.
• Masking registers are Interrupt Mask Registers

Memory Map
• The build-in peripherals (interrupt controller, debug)
these are accessed by simple memory access & also
have pre-defined memory map.
• By using C program which is easy to integrate on
SOC and speeder to access them.
• 4GB memory space
• Internal bus infrastructure structure are optimized.
• Data memory can also be executed into code region
– ......ClassblockTrans.s
• Program can be executed from external RAM region
as-well.

Memory space

Bus interface
• Fetching data and instruction is at a time – has
several bus interface. Mainly three
– Code memory bus
– System bus
– Private peripheral bus

Code memory buses
• Code memory region are accessed by code
memory bus
• Physically has two buses
– I-Code
– D-Code
• These are optimized for instruction fetches for
best instruction execution speed.

System bus
• Gives access to memory and peripherals.
• Access for
– SRAM
– Peripherals
– External RAM
– External devices
– Memory regions at system level.

Private Peripheral Bus
• These buses are reserved to access the private
peripherals bus such as debugging
components.
• Access to a part of system level memory.

MPU
• This unit is used to provide the security to selected
memory area based on rules.
• If rules are violated a code fault is generated if possible
MPU will correct or fault is pop to user.
• In OS, it sets the MPU to protect OS data shouldn’t be
accessed by other application.
• It makes some memory slots as READ-ONLY to prevent
erase of data.
• Memory isolation for numerous tasks in multitasking
system.
– Scenario is two nuclear plants with shared memory.
– Problem is staled information of temperature.

Instruction Set
• Cortex M3 supports Thumb 2 instruction set which
allows both 16 and 32 bit
• Previous ARM processor has two operating state 32 bit
and 16 bit
– 32 bit can execute all instruction with full power
– 16bit has higher instruction code density but doesn’t
support all the functionality of ARM.
• For some applications both 16 and 32 bit instructions
are mixed
– Overhead are
• Compilation should performed separately.
• Switching between states which increase code length as well

Switching of thumb to arm & vice
versa

Advantage of cortex M3 instruction set
• No state switching overhead, saving both execution time
and instruction space.
• No need to separate ARM code and Thumb code source
files, making software development and maintenance
easier.
• Has many interesting and powerful instruction
– UFBX, BFI, and BFC- Bit field extract, insert, and clear
instructions
– UDIV and SDIV
– WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and
Send-Event; these allow the processor to enter sleep mode and
to handle task synchronization on multiprocessor systems
– MSR and MRS – Move from general purpose to special register
and vice versa.

CORTEX M3 supporting instructions
• It supports only thumb 2 instruction- already
previous ARM program need to change for
new architecture.
• It doesn’t support SIMD and few thumb
instructions such as BLX( branch with link and
exchange) , SETEBD (SET ENDIAN) , some
change process state (CPS).

Interrupts and Exceptions
• It has a exception model, introduced in the
ARMv7-M architecture.
• System exceptions and external Interrupt
requests
• There is no fast interrupt but nester interrupt,
priority are supported
• Features
– Not only external, internal interrupts are also
supported such as system fault handling.
– Predefined exceptions.

Predefined exceptions

Low Power and High Energy Efficiency
• One important feature is low power is
performed using sleep and deep sleep mode.
• Low gate count and design techniques reduces
the circuit activity which in turn reduces
consumption of active power.
• Processing time is short and code size is less.
• Wakeup Interrupt Controller- sleep to awake
mode almost immediate. Hence for ultra low
power application these are used.

Debugging Support
• Debugging Features
– Program execution control those are
• Halting,
• Stepping,
• Breakpoints,
• Trace,
• Data watchpoints, register and memory access.
• Coresight Architecture is employed in CORTEX
M3. As previous ARM Cortex also doesn’t
JTAG(Joint Test Action Group)

Conti.
• Instead of JTAG, a bus interface called as DAP
(Debug Access Port) connected to core.
• Through this bus interface external debugger
can debug the hardware even the processor is
running.
• The control of this bus interface is carried out
by a Debug Port (DP) device.
• DPs has Serial Wire JTAG Debug Port

Conti.
• A JTAG-DP or SW-Dp manufacture can choose
one among this for debug interface.
• Other complier Embedded Trace Macrocell
allows instruction to trace through Trace Port
Interface Unit.
• The debug host (Computer) collected
executed instructions information via external
trace capturing hardware. Architecture of ARM Cortex M3

Conti.
• Inside a controller debug is supported by
various blocks such as breakpoints,
watchpoints, fault conditions or external
debug request input.
• When debug occurs the processor (Cortex M3)
goes to halt or execute debug monitor handler

Data watchpoint
• This function is provided by Data Watchpoint
and Trace unit in Cortex M3
• Used for
– To stop the processor
– To generate data trace information
• Example : register value or memory update
• When trace is used the traced data is
outputted via Trace Port Interface Unit

Conti.
• Flash Patch and Breakpoint (FPB)- provide a simple
breakpoint function or remap an instruction access
from Flash to a different location in SRAM
• Instrumentation Trace Macrocell (ITM) provides a new
way to output data to a debugger. By writing data to
register memory in the ITM, a debugger can collect the
data via a trace interface and display or process them.
• This method is easy to use and faster than JTAG output.
• All these debugging components are controlled via DAP
interface bus and trace information are fetched from
TPIU.

Features of Debug
• Supports JTAG or serial Wire debug interfaces
• Memory or processor status are accessed during
core running as well
• Built in support for six breakpoints and four
watchpoints
• Optional Embedded Trace Macrocell
• Data trace using Data Watchpoint and Trace
• Four watchpoints and six breakpoints hardware
• Fault status register, new fault exceptions and
flash patch operations.

Stack Push and POP

Special Registers with Programs
• Stack pointer (SP)(R13) decrements when new data is
stored and incremented when data is re-stored
– PUSH {R0} ; R13=R13-4, then Memory[R13] = R0
– POP {R0} ; R0 = Memory[R13], then R13 = R13 + 4
• PUSH, POP is used to save register contents to stack
memory at start of exception and restore when
exception ends.
• Can use multiple registers
– PUSH {R0-R7, R12, R14} ; Save registers
– POP {R0-R7, R12, R14} ; Restore registers
– BX R14 ; Return to calling function

Programming for link register (R14)
• main ; Main program
...
BL function1 ; Call function1 using Branch with Link
instruction. ; PC = function1 and
; LR = the next instruction in main
...
function1
... ; Program code for function 1
BX LR ; Return

Special Register
• These are accessed by MSR and MRS
• MRS <reg>,<special_reg> ; read special reg
• MSR <Special_reg>,<reg>; write to special reg

Program Status Registers
• MRS r0, APSR ; Read Flag state into R0
• MRS r0, IPSR ; Read Exception/Interrupt
• MRS r0, EPSR ; Read Execution state
• MSR APSR, r0 ; Write Flag state
• EPSR and IPSR are read only
• APSR is writable (can change)
• When all are accessed as a collective item, the
name xPSR is used.

PSR in the Cortex-M3.
Combined Program Status Registers (xPSR) in the Cortex-M3.

PSR in Older ARM
MOV R0 , PSR ; while accessing combined PSR

Uses of Interrupt Masking
• PRIMASK (1 bit) and BASEPRI (8-bit) -
temporarily disabling interrupts. Default value
is 0 ( no masking is there)
• FAULTMASK – used by OS during temporarily
disable fault handling when a task has
crashed. (1-bit)
• During a crash there will be different faults,
the OS kernel needs time to clear these and
during that no interrupts should be generated.

Functions created based on vendors
(all companies differ this structure)
• x = __get_BASEPRI(); // Read BASEPRI register
• x = __get_PRIMARK(); // Read PRIMASK register
• x = __get_FAULTMASK(); // Read FAULTMASK register
• __set_BASEPRI(x); // Set new value for BASEPRI
• __set_PRIMASK(x); // Set new value for PRIMASK
• __set_FAULTMASK(x); // Set new value for FAULTMASK
• __disable_irq(); // Clear PRIMASK, enable IRQ
• __enable_irq(); // Set PRIMASK, disable IRQ

In assembly
• MRS r0, BASEPRI ; Read BASEPRI register into R0
• MRS r0, PRIMASK ; Read PRIMASK register into R0
• MRS r0, FAULTMASK ; Read FAULTMASK register into R0
• MSR BASEPRI, r0 ; Write R0 into BASEPRI register
• MSR PRIMASK, r0 ; Write R0 into PRIMASK register
• MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register
The PRIMASK, FAULTMASK, and BASEPRI registers cannot be set in the
user access level.

Control Register
• Used to define privilege level and the SP selection and
has two bits
• CONTROL[1] – it is always 0 in handler mode 1 for
thread or base level i.e. it is writable only in thread
mode
– used for knowing stack
• 1- alternate stack
• 0 – default stack (MSP)
• No alternate stack can be used when its in handler mode
• In thread or base level the alternate stack PSP is chosen
• CONTROL[0] – writable only in privileged state, if it
enters user state a interrupt should be generated to get
back to privileged state.

Access controller register
• In C
– x = __get_CONTROL(); // Read the current value of
CONTROL
– __set_CONTROL(x); // Set the CONTROL value to x
• In assembly
– MRS r0, CONTROL ; Read CONTROL register into R0
– MSR CONTROL, r0 ; Write R0 into CONTROL register

EXCEPTION & INTERRUPTS
• Cortex M3 supports a fixed number of
exceptions and interrupts (IRQ)
• Interrupts number are decided by
manufacturer
• Interrupts are generated by peripherals.
• Typical number of interrupts are 16 or 32
many Micro-controller are lesser or greater.

Non-Maskable Interrupt
• Use of NMI are different in different vendors
• Most of the applications NMI is connected to
watchdog timer or voltage monitoring blocks
– voltage-monitoring block that warns the processor
when the voltage drops below a certain level.
– NMI are activated at any time as they are next to
reset.

Exceptions Types

Vector Table
• Whenever the exceptions occurs, corresponding
handler is executed by using starting address of it
stored in vector table.
• The vector table is an array of word data inside
the system memory, each representing the
starting address of one exception type.
• Vector table are re-locatable and it is performed
by NVIC
• After reset, this relocation control register is
reset to 0; therefore, the vector table is located in
address 0x0 after reset.

Example
• How the addressing is made
– Exceptions starts after reset
– In reset the vector table value is 0
– Exception 1 = 4 times the address of reset vector
– Exception 2 = 4 times the address of exception 1
– Here 4 is each word has 4 bytes.

Vector Table

Stack Operation
• Have two types one is ascending stack and
another one is descending stack
– We use descending one SP decrements before store
• Push of single register and corresponding pop
• Pushing multiple registers and pop.
• Pushing and pop without return
– Push the contents of registers and link register
– Pop the same and feed the address of link register to
PC

Single register in PUSH/POP

Multiple Register PUSH/POP

Without Return (Branch)

Two stack Model
• We know that stack has two models one is
– MSP ( Main Stack Pointer)
– PSP (Processor Stack Pointer)
• Control register are used to switch between
them Control [1] – 0 MSP

Thread and Handler use Main Stack

Thread mode used PSP and Handler
MSP

Reset Sequence
• When resets, core reads as follows
– Starting address of R13 ( SP)
– Reset vector (starting address of program
execution)

Initial Stack Pointer Value and Initial PC
as Example

THANK YOU

Module 1 - ARM 32 Bit Microcontroller

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