Module 2 ARM CORTEX M3 Instruction Set and Programming

ARM Cortex M3 Instruction Sets
and Programming
Prof. Amogha B
Asst. Prof.
JIT, Davangere.

Why Assembler
5/22/2018 Dept. of ECE, JIT, DVG 2
• Most industrial microcontroller users program
in assembly language
• Many MC users will continue to program in
assembly they need the detailed control flow
• Many application require the efficiency of
assembly language
• Understanding the assembly helps in
evaluating high level language.

Outline
• Assembly basics, Instruction
• List and description,
• Useful instructions,
• Assembly and C language Programming
5/22/2018 3Dept. of ECE, JIT, DVG

Introduction
• It focus on the various instruction set of
CORTEX M3 and example for each

Assembly Basics
• The basic syntax should be clearly understood before
writing the programs
• Common syntax is
– Label opcode operand1, operand2,…… ; comments
• Label is optional for every instruction
– Address of instruction are identified by label.
• Opcode – a high level English word for user and
machine level code for computers
• Normally first operand is destination and it depends on
instruction.
• Number of operands are dependant on instruction.

Example moving a immediate data
• Mov r0, #0x12 ; after execution r0 = 0x12 (H)
• Mov r1,#’A’ ; after execution r1= ASCII value.
– While passing ASCII inside codes or 0xA is good
• The text after ; is considered as comments
which doesn’t effect the execution which
helps the user to understand the code in
better way.

EQU
• It is used to define the constants and they can
be used inside the program.
• Example : keil

DCB, DCD
• Constants are stored in the literal pool
– Literal pool means a portion of memory
embedded in the code to hold constant values
– Constant values are placed at the address near to
end
• DCB – define constant byte to store characters
• DCD- define constant data in binary format
• Example

Use of Suffixes
• In assembler for ARM processors, instructions can
be followed by suffixes.
• In Cortex M3 the conditional execution suffixes
are usually used for branch instructions.
• The suffixes are
– S – Update Application Program Status Register (APSR)
ex: ADDS R0, R1; updates APSR
– EQ, NE, LT , GT – conditional execution
• ex: BEQ <Label> ; Branch if equal.

Simple Addition Program
• 10+9+8+7+6+5+4+3+2+1+0
• 1+2+3+4+5+6+7+8+9+10

Unified Assembler Language (UAL)
• For easy porting between the thumb and ARM
code the UAL made a common syntax
– Traditional Thumb instruction : ADD R0, R1 ;
– UAL syntax : ADD R0, R1, R1; R0 = R0+R1
• Thumb syntax can be used, in assembly
directive to make differentiate between the
thumb and UAL syntax are mentioned.
– CODE 16 – traditional Thumb
– THUMB – UAL syntax

Conti.
• Developer should be careful while using
Traditional thumb as some updates APSR
• Where as in UAL syntax if S is used then only it
updates the APSR
– AND R0, R1 ; Traditional Thumb syntax
– ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is
added)

Some instruction can done in THUMB
and THUMB-2
• The .W (wide) suffix specifies a 32-bit instruction.
If no suffix is given, the assembler tool can
choose either instruction but usually defaults to
16-bit Thumb code to get a smaller size
– ADDS R0, #1 ; Use 16-bit Thumb instruction by
default ; for smaller size
– ADDS.N R0, #1 ; Use 16-bit Thumb instruction
(N=Narrow)
– ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction
(W=wide)

Conti.
• In C compliers will use 16 bit instructions if data
size is less and switches to thumb2 if exceeds
• R0 – R7 can be accessed by thumb
• No limitations for register accessing for thumb 2
• Location for thumb 2 and thumb
– 0x1000 : LDR r0,[r1] ;a 16-bit instructions (occupy
0x1000-0x1001)
– 0x1002 : RBIT.W r0 ;a 32-bit Thumb-2 instruction
(occupy; 0x1002-0x1005) – 4 bytes

Instruction List
• 16 Bit Data Processing Instruction
• ADDITION
– ADC
– ADD
– ADR
• Compare
– CMP
– CMN- compare negative compare one data with two’s
complement of another data and update flags

Instructions
• AND
• BIC performs an AND operation on the bits
in Rn with the complements of the
corresponding bits in the value of Operand2.
• CPY – copy instruction same as mov i.e data
transfer between two register
• MVN – perform not operation
• NEG- 2’s compliment

16 Bit Data Processing Instruction

Branch Instruction
• B Branch
• B<cond> Conditional branch
• BL Branch with link; call a subroutine and store the
return address in LR (this is actually
• a 32-bit instruction, but it is also available in Thumb in
traditional ARM processors)
• BLX Branch with link and change state (BLX <reg> only)
• BX <reg> Branch with exchange state
• CBZ Compare and branch if zero (architecture v7)
• CBNZ Compare and branch if nonzero (architecture v7)
• IT IF-THEN (architecture v7) – in next slides will see this

CBZ AND CBNZ
• The branch destination must be within 4 to 130 bytes
after the instruction and in the same execution state.
• These instructions must not be used inside an IT block.
• Condition flags
– These instructions do not change the flags.
• Architectures
– These 16-bit Thumb instructions are available in ARMv6T2
and above.
– There are no ARM or 32-bit Thumb versions of these
instructions.

CBZ
• Same as
– CMP R0, #0
– BEQ LABEL

16 BIT LOAD AND STORE INSTRUCTION
• LDR Load word from memory to register
• LDRH Load half word from memory to register
• LDRB Load byte from memory to register
• LDRSH Load half word from memory, sign extend it, and put it in
register
• LDRSB Load byte from memory, sign extend it, and put it in register
• STR Store word from register to memory
• STRH Store half word from register to memory
• STRB Store byte from register to memory (Only LSB)
• LDM/LDMIA Load multiple/Load multiple increment after
• STM/STMIA Store multiple/Store multiple increment after
• PUSH Push multiple registers
• POP Pop multiple registers

Other 16 bit Instruction
• SVC Supervisor call
• SEV Send event
• WFE Sleep and wait for event
• WFI Sleep and wait for interrupt
• BKPT
– Breakpoint; if debug is enabled, it will enter debug mode(halted), or if debug
monitor exception is enabled, it will invoke the debug exception; otherwise, it
will invoke a fault exception
• NOP No operation
• CPSIE
– Enable PRIMASK (CPSIE i)/FAULTMASK (CPSIE f ) register (set the register to 0)
• CPSID
– Disable PRIMASK (CPSID i)/ FAULTMASK (CPSID f ) register (set the register to1)

32 bit Data processing
• PDF on Desktop
• UXTB – unsigned extend byte
– B- byte for 16 bit
• UXTH – unsigned extend half word
• UBFX - Signed and Unsigned Bit Field Extract.
– Copies adjacent bits from one register into the least significant bits of a
second register, and sign extends or zero extends to 32 bits.
• UBFX/SBFX{cond} Rd, Rn, #lsb, #width
• USAT – saturates to in range of unsigned number
• LDREX
– If the physical address has the Shared TLB attribute, LDREX tags the physical
address as exclusive access for the current processor, and clears any exclusive
access tag for this processor for any other physical address.

Unsupported Thumb Instructions
• Unsupported instructions are
– Coprocessor are not supported
– The two instructions that cortex M3 doesn’t
support are BLX, SETEND
– Unsupported Change Process State Instruction
• If these are invoked a usage fault exceptions
will generate.

Unsupported Thumb Instructions
• BLX label
– This is branch with link and exchange state. In a format
with immediate data, BLX always changes to ARM state.
Because the Cortex-M3 does not support the ARM state,
instructions like this one that attempt to switch to the
ARM state will result in a fault exception called usage fault.
• SETEND
– This Thumb instruction, introduced in architecture v6,
switches the endian configuration during run time. Since
the Cortex-M3 does not support dynamic endian, using the
SETEND instruction will result in a fault exception.

Unsupported Co-Processor
• MCR Move to coprocessor from ARM processor
• MCR2 Move to coprocessor from ARM processor
• MCRR Move to coprocessor from two ARM register
• MRC Move to ARM register from coprocessor
• MRC2 Move to ARM register from coprocessor
• MRRC Move to two ARM registers from coprocessor
• LDC Load coprocessor; load memory data from a
sequence of consecutive memory addresses to a
coprocessor
• STC Store coprocessor; stores data from a coprocessor
to a sequence of consecutive memory addresses

Unsupported Change Process State
Instructions
• CPS<IE|ID>.W A There is no A bit in the Cortex-
M3
• CPS.W #mode There is no mode bit in the Cortex-
M3 PSR
– A- abort
– I- interrupt
– T- Thumb state
C:UsersAmoghaDesktopProgram+Status+Registers
.jpg

Unsupported Hint Instructions
• Used in the place of below instruction
– NOP, WFE, WFI, YIELD, SEV-set event
• DBG A hint instruction to debug and trace system
• PLD Preload data; no cache on cortex M3
• PLI Preload instruction; no cache on cortex M3
• YIELD
– A hint instruction to allow multithreading software to
indicate to hardware that it is doing a task that can be
swapped out to improve overall system performance.

Instruction Descriptions
• Moving Data
– Moving data between register and register
– Moving data between memory and register
– Moving data between special register and register
– Moving an immediate data value into a register

Moving data between register
• The instruction used is MOV
– MOV R5,R3 ; R3 contents are moved to R5
• If need to generate negative value of original
data is MVN

Moving an Immediate data Value to
Register
• The instruction used is MOV
• MOV R0,#0x123
– Important thing is the immediate value should be
less than 16 bits

LOAD / STORE instruction
• Load from memory to register
• STORE- register to Memory

Pre and post Indexing of memory

Moving data between memory and
register
• The instruction used for performing this are
LOAD and STORE
– LOAD (LDR)
– STORE (STR)
• The transfer of data is of different data size
– Byte, half word, word etc
• Multiple data are combined and
stored/accessed from memory

Move of special register to register
• MSR
– MOV xPSR,R0
• MRS
– MOV R0,APSR

Processing DATA
• There are many data processing operations in
cortex M3, can have multiple instruction
formats
– Ex: ADD; instruction can operate between two
registers or between one register and an
immediate data value
– ADD R0, R0, R1 ; R0 = R0 + R1
– ADDS R0, R0, #0x12 ; R0 = R0 + 0x12
– ADD.W R0, R1, R2 ; R0 = R1 + R2

Traditional Thumb and Thumb2
• The only difference between them are
– Traditional thumb instruction updates flag without
specifying by user
– Thumb2 if user specified then only those
instructions can update flags.

Instruction Operation
ADD RD, RN,RM ; RD=RN+RM Perform addition
ADD Rd, #immed ; Rd = Rd + #immed
ADD Rd, Rn, # immed ; Rd = Rn + #immed
ADC Rd, Rn, Rm ; Rd = Rn + Rm + carry
ADC Rd, Rd, Rm ; Rd = Rd + Rm + carry
Addition with carry
ADDW Rd, Rn, #immed ; Rd = Rn +
#immed
ADD register with 12-bit immediate value
Same for subtraction immediate, subtract
with barrow SUB, SBC,
SUB Rd, Rn, Rm ; Rd= Rn -Rm Subtract
RSB.W Rd, Rn, Rm ; Rd = Rm – Rn Reverse Subtract
MUL Rd, Rn, Rm ; Rd = Rn*Rm Multiply
UDIV Rd, Rn, Rm Division for unsigned division SDIV -signed

Other instruction
• Multiplication – signed and unsigned
• Logic operation –
– AND, ORRR, EOR(EX-OR), BIC(Bit clear)
• Shift and rotate
– Logical Shift Left
– Logical Shift Right
– Rotate Right
– Arithmetic Shift Right (ASR)

Shift and Rotate

• ASR It copies the sign bit into vacated bit positions on
the left.
• LSL provides the value of a register multiplied by a
power of two.
• LSR provides the unsigned value of a register divided
by a variable power of two. Both instructions insert
zeros into the vacated bit positions.
• ROR provides the value of the contents of a register
rotated by a value. The bits that are rotated off the
right end are inserted into the vacated bit positions on
the left.
• RRX provides the value of the contents of a register
shifted right one bit. The old carry flag is shifted into
bit[31]. If the S suffix is present, the old bit[0] is placed
in the carry flag.

Logical Operations
• AND gate
– AND Rd, Rn ; Rd = Rd & Rn
– AND.W Rd, Rn, Rm ; Rd = Rn & Rd for 32 bit
• OR gate
– ORR Rd, Rn ; Rd = Rd | Rn
– ORR.W Rd, Rn, Rm ; Rd = Rn | Rd
• Bit clear and Exor gate
– BIC Rd, Rn ; Rd = Rd & (~Rn)
– EOR Rd, Rn ; Rd = Rd ^ Rn
• Bit wise OR and NOT
– ORN.W Rd, Rn,#immed ; Rd = Rn | (~#immed)

There is no ROTATE LEFT
• Only a rotate right is provided
• The rotate right can be operated as left if we
increase the rotation value.

Sign Extend Instruction
Instruction Operation
SXTB Rd, Rm ; Rd = signext(Rm[7:0]) Sign extend byte data into word
SXTH Rd, Rm ; Rd = signext(Rm[15:0]) Sign extend half word data into word

Reverse Operation

Call and Unconditional Branch
• Posses three statements
– Branch with label ex: B label
– Branch to specified address: BX REG
– Branch to link : BL

Decisions and Conditional Branches
• Flags
– N- Negative
– Z- zero
– C- carry This flag is for unsigned data processing for
example, in add (ADD) it is set when an overflow
occurs; in subtract (SUB) it is set when a borrow did
not occur (borrow is the invert of carry)
– V- Over flow
• BEQ label or BEQ.W label; branch to label address
when zero flag is set

Symbol Condition Flag
CS/HS Carry set/unsigned higher or same C –set
CC/LO Carry clear/unsigned lower C – clear
MI Minus/negative N- set
PL Plus/Positive or zero N-clear
VS Overflow V-set
VC No overflow V-clear
HI Unsigned higher C- set and Z clear
LS Unsigned Lower or same C-clear or Z set
GE Signed greater than or equal N set and V set, or N clear and V clear (N
== V)
LT Signed Les than N set and V clear, or N clear and V set (N
!= V)
GT Signed Greater than Z clear, and either N set and V set, or N
clear and
V clear (Z == 0, N == V)
LE Signed Less than or equal Z set, or N set and V clear, or N clear and
V set (Z == 1 or N != V)
AL/
EQ/NE
Always( Un-conditional), equal and not
equal5/22/2018 Dept. of ECE, JIT, DVG 49

TST
• TEST instruction is same as AND, it performs
AND, updates flags but doesn’t store results.
– TST R0, R1 ; Calculate R0 AND R1 and update
flag
– TST R0, #0x12 ; Calculate R0 AND 0x12 and update
flag

Syntax for IT (TRUE- THEN-ELSE)
• IT<x><y><z> <cond>; IT instruction (<x>, <y>, ; <z> can be T or E)
• instr1<cond> <operands> ; 1 instruction (<cond> ; must be same as
IT)
• instr2<cond or not cond> <operands> ; 2 instruction (can be ; <cond> oe
<!cond>
• instr3<cond or not cond> <operands> ; 3 instruction (can be ;<cond> or
<!cond>
• instr4<cond or not cond> <operands> ; 4instruction (can be ; <cond> or
<!cond>

Program on IT
• Less than 4 instructions are executed and
minimum is 1.
• The number of instructions should be maintained
• During exception
– Single IT – exception are stored in PSR and pop when
exception is served
– Multiple instructions ( multiple load and store) the
whole instructions are abandoned and restarted( 1st IT
instruction) after interrupt process is completed.

Memory Barrier
• Avoids occurring of race conditions during
memory errors.
• Whenever the memory misses in cache previous
controller will wait till the memory corrects but
now if the result of present line is not dependent
on next instruction then the ARM will proceed for
executing the next line
– Ex: LDR r0, [r1] if error occurs in load
– STR r2,[r5] here store isn't depending on load hence
arm executes the same.

Registers for Memory Barrier
• DMB Data memory barrier; ensures that all
memory accesses are completed before new
memory access is committed
• DSB Data synchronization barrier; ensures that all
memory accesses are completed before next
instruction is executed
• ISB Instruction synchronization barrier; flushes
the pipeline and ensures that all previous
instructions are completed before executing new
instructions

Saturation Operations

• SSAT.W <Rd>, #<immed>, <Rn>, {,<shift>}
Saturation for signed value
• USAT.W <Rd>, #<immed>, <Rn>, {,<shift>}
Saturation for a signed value into an unsigned value
– Rn: Input value
– Shift: Shift operation for input value before
saturation; optional, can be #LSL N or #ASR N
– Immed: Bit position where the saturation is carried
out
– Rd: Destination register

Unsigned Saturation Operation

Division
• SDIV
– SDIV{cond} {Rd}, Rn, Rm
• UDIV
– The result is Rd = Rn/Rm.
• Code
• LDR R0,=300 ; Decimal 300
• MOV R1,#5
• UDIV.W R2, R0, R1

Divide by zero
• You can set up the DIVBYZERO bit in the NVIC
Configuration Control Register so that when a
divide by zero occurs, a fault exception (usage
fault) takes place. Otherwise, <Rd> will
become 0 if a divide by zero takes place.

Table Branch Byte
• Table Branch Byte (TBB) and Table Branch
Halfword (TBH) are for implementing branch
tables. The
• TBB instruction uses a branch table of byte
size offset, and TBH uses a branch table of half
word offset.
– Syntax: TBB.W [Rn, Rm]

Example IF-THEN-ELSE
• CMP R0, R1 ; Compare R0 and R1
• ITTE GT ; If R0 > R1 Then ; if true, first 2
statements execute,
; if false, other 1 statement is executed
• MOVGT R2, R0 ; R2 = R0
• MOVGT R3, R1 ; R3 = R1
• MOVLE R2, R0 ; Else R2 = R1

Program
• IT PROGRAM
• IF CONDITION IS TRUE
– Perform Three operations
• If Condition is false
– Perform two operations
• Condition be like compare R1 and R2.
– Condition is if (R1 < R2)

Memory System Features
• Features
– Predefined memory map for bus interface these
are enabled when memory location is accessed
– This feature allow the porting between the
processor and it is made easy
– Bit band access – each bits can be addressed using
bit-band example 0x20000004
– Unaligned transfers of data
– Supports both little endian and big endian
memory configuration

Memory Maps
• CORTEX M3 has the fixed memory map which
makes software porting to another product
– System peripherals (NVIC, MPU) have same
location for all CORTEX M3 hence manufactures
can differentiate with others.
– Some memory locations are reserved to private
peripherals such as debugging components.
Private peripheral memory region holds this

Private peripheral components
• Fetch patch and break point unit (FPB)
• Data watch-point and trace unit (DWT)
• Instrumentation Trace Macrocell (ITM)
• Embedded Trace Macrocell (ETM)
• Trace Port Interface Unit (TPIU)
• ROM table –
– Shows the minimum size of ROM required to contain
the image (ext. data video, audio, image). This does
not include ZI data and debug information which is
not stored in the ROM.

ADDRESS SPACE
• 4GB of address space
• Program code can be placed in
– Code region
– Static Random Access Memory region
– External RAM region
• Preferably the codes are placed in code
regions as data fetching can happen
simultaneously on two separate bus.

SRAM Memory range
• SRAM memory range is for connecting
internal SRAM, system interface bus is used for interface.
• 32 MB is defined as a bit band alias.
– A 32-bit-band alias memory range, each word
address represents a single bit in the 1-MB bit-
band region
– For altering the bit band alias we can use atomic
READ-MODIFY-WRITE.
– Bit band alias memory access works only for data
not for instruction fetches.

On chip peripherals
• 0.5 GB block of address range is allocated to
on-chip peripherals.
• This is also supports bit band alias for
modifying
• Instruction execution is not allowed in this
region.

External RAM
• Two slots of 1-GB memory space are allocated
for external RAM and external devices.
• Normally program won’t execute in memory
reserved for external device.
• If required in external RAM is attached

AMBA bus
• 0.5 GB at last is reserved for system level
components , internal peripheral buses, external
peripheral bus, and vendor-specific system
peripherals.
• Private peripheral bus – two segments
– Advanced high Performance Bus (AHB)- for Cortex-
M3 internal AHB peripherals only like NCIV.
– Advance Peripheral BUS (APB)- for internal APB and
external peripherals.
• A provision is provided in CORTEX M3 additional on chip APB
which is provided in private peripheral bus via APB interface.

System level
• The NVIC is located in a memory region called
the system control space (SCS)
– Additional interrupt control features, this region
also provides the control registers for SYSTICK,
MPU, and code debugging control.

• Question paper discussion

Yesterday
• Every peripheral is reserved by address and it
is accessible
• Bit band operation – for read write operation

Memory Access Attributes
• The CORTEX M3 memory attributes (Method) are
– Bufferable:
• Write to memory can be carried out by a write buffer while the
processor continues on next instruction execution. Example : UART
– Cacheable:
• Data obtained from memory read can be copied to a memory
cache so that next time it is accessed the value can be obtained
from the cache to speed up the program execution
– Executable
• Processor can execute code from this memory region
– Sharable
• Data in this memory region could be shared by multiple bus
masters

Memory regions of attributes
• Code Memory region (0x00000000 to 0x1FFFFFFF)
– Region is executable
– Cache is write through i.e. can have data in this
memory region
– Data is transferred using the data bus interface
– Write transfers is bufferable

CONTI.
• SRAM memory region (0x20000000–0x3FFFFFFF)
– Meant for on-chip RAM
– Executing the code is feasible.
– Write transfer are bufferable.
• Peripheral Region (0x40000000–0x5FFFFFFF)
– Reserved to use only by peripherals
– Can’t execute program here
• External RAM (0x60000000–0x7FFFFFFF)
– Used for on or off chip memory
– Can execute the program in this region
– Write data are bufferable

Conti.
• External RAM (0x80000000–0x9FFFFFFF)
– Reserved only for external devices
– Memory is non-bufferable to access
– Can’t execute code in this region
• Same for 0xC0000000–0xDFFFFFFF
• System Region (0xE0000000–0xFFFFFFFF)
– Reserved for the usage of private peripherals and
vendor specific peripherals
– For private peripherals access are non-bufferable
– Vendor specific access are bufferable

Default Memory Access Permission
• Prevents the user programs to access some
locations which are controlled by MPU
Memory
Region
Address Access in User Program
Vendor Specific 0xE0100000–0xFFFFFFFF Full access
ROM table 0xE00FF000–0xE00FFFFF Blocked ; if user tries to access a bus
fault is generated
External Private
Peripheral Bus
0xE0042000–0xE00FEFFF Blocked; if user tries to access a bus
fault is generated
ETM
(Embedded
Trace
Macrocell)
0xE0041000–0xE0041FFF Blocked; if user tries to access a bus
fault is generated

TPIU Trace Port Interface
Unit
0xE0040000–0xE0040FFF Blocked; if user tries to
access a bus fault is
generated
Internal Peripheral Private
Bus
0xE000F000–0xE003FFFF Blocked; if user tries to
generated
NVIC 0xE000E000–0xE000EFFF Blocked; if user tries to
generated
FPB 0xE0002000–0xE0003FFF Blocked; if user tries to
generated
DWT 0xE0001000–0xE0001FFF Blocked
ITM 0xE0000000–0xE0000FFF Blocked
External device 0xA0000000–0xDFFFFFFF Full Access
External RAM 0x60000000–0x9FFFFFF Full Access
Peripheral 0x40000000–0x5FFFFFFF Full Access
SRAM 0x20000000–0x3FFFFFFF Full Access
Code 0x00000000–0x1FFFFFFF Full Access5/22/2018 Dept. of ECE, JIT, DVG 80

Un-Alignment Basics
Programmers see memory as just a row of memory array
Process see memory in union of even numbers 4,8,16,32

Aligned access
Consider reading a 4 Byte
of data
Data should be aligned to
4,8,16,32 formats , if not
we are not going to get
accurate fetching

Unaligned Data access

UNALIGNED TRANSFERS
• Supports both unaligned and aligned access
• Traditional ARM were supporting only aligned
memory access
• 1 bytes = ?
• 8 bit
• If 32 bits – 4 bytes of memory
• 16- 2 bytes
• 8- 1 bytes

Example for unaligned data
For full word (32)
For half word (16)

Exclusive Accesses
• In CORTEX M3 we don’t have swap option
instead of it we posses exclusive access.
• Swapping was normally used in semaphores
– Semaphores are used to allocate shared resources
to applications.
– Shared source serve only one application at a time
i.e. called as Mutual Exclusion (MUTEX).
– If the resource is being locked by one process
(task), it can’t serve another process until the lock
is released

Conti.
• MUTEX semaphore in memory is used to
indicate whether the resource is locked or
free.

Working

Programming it
• Cortex-M3 include LDREX (word), LDREXB
(byte), LDREXH (half word), STREX (word),
STREXB (byte), and STREXH (half word
• Rxf – base register address with shifted offset
value
• LDREX <Rxf>, [Rn, #offset]
• STREX <Rd>, <Rxf>,[Rn, #offset]

Endian mode
• Cortex M3 supports both little endian and big
endian mode
• Little endian mode
– LSB Data = MSB of memory
– Data 0x12345678
– Address 0x40000010 – 78 56 34 12

Figure

Big Endian
– Data 0x12345678
– Address 0x40000010 – 12 34 56 78

Big Indian Memory Example

Conti.
• The endian mode is set when the processor
exits reset later it can’t be changed.
• No dynamic changing of memory mode
• If processor is in little endian, some
peripherals works on big endian means
change the format using REV, REV16

BIT BAND Operation
• Bit-band operation support allows a single
load/store operation to access (read/write) to
a single data bit.
• Memory regions are bit band region(1MB) and
bit band alias (32MB)
• Use of bit band is each peripheral bits can be
accessed separately in LSB.

Working
• If without bitband
– Access the address
– Load the changing value to another register
– Perform OR to modify bit
– Store the result to address.
• With bit-band
– Load address to register
– Load the changing value
– Store the modified value to address

Differences
• Without bit band
• LDR R0,=0x20000000; set address
• LDR R1,[R0] ; Read
• ORR.W R1,#0x4; modify bit
• STR R1,[R0]
• With Bit Band
• LDR R0,=0x20000008
• MOV R1,#1
• STR R1,[R0]

Example

Perform it using and not using bit band

Advantages
• During branch decisions on peripherals the
below task happens if not bit band is
– Reading whole register
– Masking the unwanted bits
– Comparing and branch
• These are simplified as
– Reading the status bit via bit-band alias
– Comparing and branching

BIT-BAND and BIT-BANG
• Bit-band to indicate that the feature is a
special memory band (region) that provides
bit accesses
• Bit bang commonly refers to driving I/O pins
under software control to provide serial
communication functions.

Data last when exception occurs if bit
band is not used

Bit band providing locking facility
during exceptions

Programming bitband
• #define DEVICE_REG0 *((volatile unsigned long *) (0x40000000))
• #define DEVICE_REG0_BIT0 *((volatile unsigned long *)
(0x42000000))
• #define DEVICE_REG0_BIT1 *((volatile unsigned long *)
(0x42000004)) ...
• DEVICE_REG0 = 0xAB; // Accessing the hardware register by normal
// address..
• DEVICE_REG0 = DEVICE_REG0 | 0x2; // Setting bit 1 without using
// bitband feature...
• DEVICE_REG0_BIT1 = 0x1; // Setting bit 1 using bitband feature //
via the bit band alias address

Development Flow

Flow of program
• Whenever the applications are developed using
cortex M3 it is the process.
• The concepts of code generation flow in terms of
these tools are similar
• Basic ones are
– Assembler
– C complier
– Linker
– Binary file generation utilities.
• Real View development suite (RVDS) or Real view
complier tools shows a file generation flow.

Flow is explained by taking C program
• Create C program
• Create vectors
• Create vector table
• Compile the file
• Use linker to link the file
• Get executable file .elf
– In Mp steps (REMEMBER MASM, LINK, CV exe)

To compile
• arm cc –c –g –W sample_LED.c –o
sample_LED.o
• armcc –c -g –W vectors.c –o vectors.o
• o- object file (remember MP programs)
• After MASM object files were created.

Linker
• LINKER used to generate the program image.
• It generates filename.scat
• scat tells the linker to put the starting address
of program into vector table

Linker Commands
• Armlink –scatter sample_LED.scat "--
keep=vectors.o(exceptions_area)“
sample_LED.o vectors.o sample_LED.ELF
• Executable image sample_LED.ELF is
generated

Execute image
• /* create binary file */
• $> fromelf –-bin sample_LED.elf –output
sample_LED.bin
• /* Create disassembly output */
• $> fromelf –c sample_LED.elf > list.txt

Compile in same example in Keil using
DOS
• C:KeilARMBIN40armcc -c -O3 -W -g -Otime
--device DLM vectors.c
• C:KeilARMBIN40armcc -c -O3 -W -g -Otime
--device DLM blinky.c
• C:KeilARMBIN40armlink --device DLM "--
keep=Startup.o(RESET)"
"--first=Startup.o(RESET)" -scatter led.scat --
map vectors.o blinky.o -o blinky.elf
• C:KeilARMBIN40fromelf --bin blinky.elf -o
blinky.bin

Accessing Memory Mapped Regions in
C
• Accessing the Peripherals using
– Volatile Pointers
– From address
– Place pointers to elements
– Scatter Loading file.

Accessing Peripheral Registers as
Pointers.
#define SYSTICK_CTRL
(*((volatile unsigned
long *) (0xE000E010)))

Alternative Way of Accessing
Peripheral Registers as Pointers.
Define address directly
# define SYSSTICK_CTRL
= 0xE000E010

Accessing Peripheral Registers as
Pointers to Elements in Data Structure

Defining Peripheral-Based Address
Using Scatter Loading File.

Intrinsic Function
• A built in function that is implemented directly
by the complier without making use of any
library

Embedded Assembler and Inline
Assembler
• Feature is provided to write the assembly
inside the C code it is called as inline
assembler.
• Format
• Type of program, return type , access

Interface assembly and C
• Tasks can’t performed in C coding
– Functions such as direct manipulation of stack
data or special is not possible
– Timing-critical routines
– Tight memory requirements, causing part of the
program to be written in assembly to get the
smallest memory size

FORMAT
• Slight change
• armasm –cpu cortex –m3 –o test1.o test1.s
• Armlink –rw_base 0x2000000 –ro_base 0x0 –
map –o test1.elf tes1.o
– Here 0x0 is the read only memory
– 0x20000000 specifies a read/write memory.
• Fromelf –bin –output test1.bin test1.elf
• Fromelf –c –output test1.list test1.elf

Producing Output

Output to console other than UART
• Semi-hoisting: we can send the output using
printf statement using debug register
• Instrumentation trace: the output is sent to
outer world using trace port analyzer
• Instrumentation trace via serial wire viewer:
other than Trace port interface unit a low cost
serial wire viewer can be used to get data

UART program in Assembly
• In C
• Logic ?
• CHECK LSR content
• Need to use Transmitter CHECK THR (0x20)
• IF Receive (0x01)
• RBR
• Assembly
• Load UART_FLAGS to one register and compare
with 0x20

All algorithm
• Main program
– Make r0 to r4 as 0
– Branch to label UART0Initialize
– Load R0 with content of variable by name NUM1
– Branch to Puts
• Puts, Putswaitloop, Putsloop exit
• Putc, Putcloop
• Uart0Intitialize label
• NUM1 deceleration

CMSIS – Newly added to the syllabus
CORTEX MC Software Interface
Standard

CORTEX M3 in embedded application
market
• By 2008, it has 5 complier vendors, more than
15 embedded Operating Systems.
• Many companies were providing hands for
embedded software solutions
– Codecs ( decoders ex: KM player some new format
of video needs to download codecs)
– Data processing libraries
– Various software and debug solutions

Aims of CMSIS
• Improve software portability and reusability
• Develop a products and device libraries which
works on various silicon vendors
• Easy to use and have standard interface
• Run on multiple sources without the risk of
drivers installation.

Organization of CMSIS

Layers
• Core Peripheral Access Layer- to access core
registers and core peripherals
• Middleware Access Layer
– A common method for accessing peripherals ( yet to
launch)
– Communication includes Ethernet, UART, SPI
– Software support for communication interface
• Device Peripheral Access layer (Microcontroller
unit specific)
• Access functions for peripherals (Microcontroller
unit specific)

CMSIS includes

• Core_CM3.h contains peripheral register definitions
and access functions
– NVIC, System Control Block registers and SYSTICK registers.
– Includes CMSIS intrinsic functions
– Includes a function to output debug message via
Instrumentation Trace Module.
• Core_cm3.c includes CMSIS intrinsic functions which
aren’t defined in Core_CM3.h
• System_Device.h- contains Microcontroller specific
interrupt number, exception and handlers.
• System <device.c> specific function of
microcontroller which includes system initialization.

Example
• #include “vendor_device.h>
– <lpc17xx.h> // NXP
– <lm3S_CMSIS.h> //Micro devices
– Stm32f10x.h // for ST devices (house hold appli.)
• SystemInit (); used for system initialize code
• Void UART1_IRQHandler - for peripherals
• Void SysTick_Handler – system handlers

Benefits of CMSIS

Thank You
• Uart_base equ 0x4000000
• Uart_flag equ uart_base+0x20
• Uart_data equ uart_base+0x40
• Area
• Mov r0,#0
• R1,r2,r3,r4
• B uart0_initilization
• BL puts

Module 2 ARM CORTEX M3 Instruction Set and Programming

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