Notes: Verilog Part 1 - Overview - Hierarchical Modeling Concepts - Basics
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This document provides an overview of Verilog, covering its high-level description to RTL conversion, design methodologies (top-down and bottom-up), and levels of abstraction (behavioral, data flow, gate, and switch levels). It includes details on Verilog modules, instances, data types, and system tasks, as well as verbal conventions and compiler directives. The information is aimed at assisting users in understanding and using Verilog effectively for hardware description and design.
Notes: Verilog Part 1 - Overview - Hierarchical Modeling Concepts - Basics
- 1. 1|Page NOTES: Verilog Part 1 1 CHAPTER 1: HDL converts Behavioural Description to RTL Description. Data Flow is decided by the designer. Logic Synthesis tool convert RTL description to Gate Level Netlist. (Gate level netlist is a description of the circuit in terms of gate and connections between them. It ensures that the circuit meets timing, area and power specifications) The layout is verified and then fabricated. 2 CHAPTER 2: 2.1 TWO DESIGN METHODOLOGIES Top Down: The main module is divided into sub modules which are further divided into leaf cells. Bottom Up: Collect all the leaf cells available with us and form the higher level modules, and reach the main module. (WHAT IF THE BASIC MODULE IS NOT AVAILABLE WITH US?) 2.2 FOUR LEVELS OF ABSTRACTIONS Behavioural/Algorithmic level: Highest level of abstraction. Module can be designed on desired algorithm without concerning about hardware implementation. Dataflow Level: Module is designed by specifying the data flow. Gate Level: Module is implemented in terms of logic gates and interconnections. Similar to gate logic diagram. Switch Level: Module can be implemented using switches, storage nodes and interconnections between them. Lowest Level of Abstraction. 2.3 MODULES IN VERILOG ARE SIMILAR TO THE CLASSES IN C++ 2.4 INSTANCE IN VERILOG ARE SIMILAR TO THE OBJECTS IN C++ 2.5 STIMULUS AND DESIGN BLOCK. Notes: Verilog Part-1 In the first style the stimulus block instantiates the design block and directly drives the signals in the design block. The second style instantiates both stimulus and design blocks in top level dummy module. The stimulus block interacts with the design block only at through the interface. Prepared By: Jay Baxi
- 2. 2|Page 2.6 STIMULUS BLOCK IS ALSO CALLED THE TEST BENCH. 3 CHAPTER 3: 3.1 VERBAL CONVENTIONS Whitespaces: b, t, n are used for blank spaces, tabs and newlines. (WHAT IS THE NEED FOR b, IF AN ORDINARY SPACE “ “ IS USED?) Comments: //Single Line Comment /* Multi Line Comment */ Operators: j= ~b; //Unary Operator j= b && c; //Binary Operator j= b? c : d //Ternary Operator Number Specification: Sized Unknown Impedance (x) Un-sized High Impedance(z) Negative Underscore and Question Mark Strings: “a / b is a string” There are 123 keywords There are 22 system tasks and functions There are 27 compiler directives Escaped Identifiers: They begin with a backslash () and end with a white space or a new line. All the characters between a backslash and a whitespace are processed literally. 3.2 DATA TYPES: Notes: Verilog Part-1 Value Set: Value Level Condition 0 Logic Zero, False Condition 1 Logic One, True Condition X Unknown Logic Value Z High Impedance, Floating State If two signals of strong1 and weak0 contend, the result is resolved as strong1. If two signals of equal strengths contend, the result is X (unknown) Nets: They represent the connection between the hardware. In the HDL, we they are represented as wire. They are one bit values by default, unless explicitly mentioned as vectors. net is not a keyword. It is a class of data types such as wire, wand, wor, tri, triand, trior, trireg. Registers: They represent data storage elements. They retain values until other value is retained on them. Prepared By: Jay Baxi
- 3. 3|Page Unlike a net, a register does not need a driver. These registers do not need a clock unlike the hardware registers. They are used with keyword reg. And its default value is x. Vectors: wire or reg can be declared as vectors, if bit width is not specified. Operations can be performed on selected parts of the vectors. Integers: it is a register data type, reg can be used as a general purpose register but in processes like counting it is more convenient to declare them as integer. Real: real numbers are also a register data type and is declared using the keyword real. Time: Verilog simulation is done w.r.t. simulation time. A special time register is used to save the simulation time. The width of the time register data type is implementation-specific but is at least 64 bits. The system function $time is invoked to get the current simulation time. Arrays: Arrays are data types to increase the size of register data type and can be used to create multidimensional matrices. Memories: In most cases when RAMs and ROMs are designed by digital designers. For Verilog, memories are modelled as one dimensional array of registers. Each element of the array is known as the element or the word, which is of more than one bits. And is addressed by a single array index. A particular word in the memory is obtained by using the address as a memory in the subscript. Parameters: parameter allows constants to be defined in Verilog. They cannot be used as variables. Parameter values for each module instance can be overridden individually at compile time. Parameter size and type can also be defined. Strings: Strings can be stored in the reg data type. The width must be large enough to hold the string. If the width is larger than the size of the string, it fills bits to the left of the string with ZEROS. If the width is smaller than the string, it truncates leftmost bits of the string. 3.3 SYSTEM TASKS Notes: Verilog Part-1 $display: This is the main system task for displaying values of variables or strings or expressions. $monitor: This is used to monitor a signal when its value changes. $monitoron enables monitoring whereas $monitoroff disables it. $stop: The $stop task puts the simulation in an interactive mode. This is mainly used for debugging. The designer can suspend the simulation and examine the value of the signals. $finish: This terminates the simulation. Prepared By: Jay Baxi
- 4. 4|Page 3.4 COMPILER DIRECTIVES Notes: Verilog Part-1 `define: This is similar to #define construct in C. It defines text macros in Verilog. The compiler substitutes the text of the macro whenever it encounters <macro_name> ‘include: This is used to include header files or other Verilog source files which contain global or commonly used definitions. Prepared By: Jay Baxi